target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com Message-Id: <024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com>
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@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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* was called. Background registers will be used if the guest has
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* was called. Background registers will be used if the guest has
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* forced a two stage translation to be on (in HS or M mode).
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* forced a two stage translation to be on (in HS or M mode).
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*/
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*/
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if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
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use_background = true;
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}
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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mode = get_field(env->mstatus, MSTATUS_MPP);
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if (riscv_has_ext(env, RVH) &&
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MSTATUS_MPV_ISSET(env)) {
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use_background = true;
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}
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}
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}
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if (mode == PRV_S && access_type != MMU_INST_FETCH &&
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riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
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if (get_field(env->hstatus, HSTATUS_SPRV)) {
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mode = get_field(env->mstatus, SSTATUS_SPP);
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use_background = true;
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}
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}
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}
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}
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@ -608,7 +599,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
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}
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}
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break;
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break;
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case MMU_DATA_LOAD:
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case MMU_DATA_LOAD:
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if (riscv_cpu_virt_enabled(env) && !first_stage) {
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if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
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!first_stage) {
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cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
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cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
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} else {
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} else {
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cs->exception_index = page_fault_exceptions ?
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cs->exception_index = page_fault_exceptions ?
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@ -616,7 +608,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
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}
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}
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break;
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break;
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case MMU_DATA_STORE:
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case MMU_DATA_STORE:
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if (riscv_cpu_virt_enabled(env) && !first_stage) {
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if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
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!first_stage) {
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cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
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cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
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} else {
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} else {
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cs->exception_index = page_fault_exceptions ?
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cs->exception_index = page_fault_exceptions ?
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@ -706,8 +699,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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hwaddr pa = 0;
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hwaddr pa = 0;
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int prot, prot2;
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int prot, prot2;
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bool pmp_violation = false;
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bool pmp_violation = false;
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bool m_mode_two_stage = false;
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bool hs_mode_two_stage = false;
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bool first_stage_error = true;
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bool first_stage_error = true;
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int ret = TRANSLATE_FAIL;
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int ret = TRANSLATE_FAIL;
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int mode = mmu_idx;
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int mode = mmu_idx;
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@ -718,30 +709,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
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qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
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__func__, address, access_type, mmu_idx);
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__func__, address, access_type, mmu_idx);
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/*
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* Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
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* set and we want to access a virtulisation address.
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*/
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if (riscv_has_ext(env, RVH)) {
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m_mode_two_stage = env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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MSTATUS_MPV_ISSET(env);
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hs_mode_two_stage = env->priv == PRV_S &&
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!riscv_cpu_virt_enabled(env) &&
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access_type != MMU_INST_FETCH &&
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get_field(env->hstatus, HSTATUS_SPRV) &&
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get_field(env->hstatus, HSTATUS_SPV);
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}
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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mode = get_field(env->mstatus, MSTATUS_MPP);
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}
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}
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}
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}
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if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
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if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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MSTATUS_MPV_ISSET(env)) {
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riscv_cpu_set_two_stage_lookup(env, true);
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}
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if (riscv_cpu_virt_enabled(env) ||
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(riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
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/* Two stage lookup */
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/* Two stage lookup */
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ret = get_physical_address(env, &pa, &prot, address, access_type,
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ret = get_physical_address(env, &pa, &prot, address, access_type,
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mmu_idx, true, true);
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mmu_idx, true, true);
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@ -793,6 +775,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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__func__, address, ret, pa, prot);
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__func__, address, ret, pa, prot);
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}
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}
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/* We did the two stage lookup based on MPRV, unset the lookup */
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if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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MSTATUS_MPV_ISSET(env)) {
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riscv_cpu_set_two_stage_lookup(env, false);
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}
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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(ret == TRANSLATE_SUCCESS) &&
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(ret == TRANSLATE_SUCCESS) &&
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!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
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!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
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