RISC-V: Replace hardcoded constants with enum values
The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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@ -26,13 +26,10 @@
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_clint.h"
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#include "qemu/timer.h"
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#include "qemu/timer.h"
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/* See: riscv-pk/machine/sbi_entry.S and arch/riscv/kernel/time.c */
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#define TIMER_FREQ (10 * 1000 * 1000)
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static uint64_t cpu_riscv_read_rtc(void)
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static uint64_t cpu_riscv_read_rtc(void)
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{
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{
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return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), TIMER_FREQ,
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return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
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NANOSECONDS_PER_SECOND);
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SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
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}
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}
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/*
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/*
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@ -59,7 +56,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
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diff = cpu->env.timecmp - rtc_r;
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diff = cpu->env.timecmp - rtc_r;
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/* back to ns (note args switched in muldiv64) */
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/* back to ns (note args switched in muldiv64) */
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next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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muldiv64(diff, NANOSECONDS_PER_SECOND, TIMER_FREQ);
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muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
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timer_mod(cpu->env.timer, next);
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timer_mod(cpu->env.timer, next);
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}
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}
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@ -122,7 +122,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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@ -131,7 +132,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_CLOCK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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@ -115,7 +115,8 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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@ -124,7 +125,8 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SPIKE_CLOCK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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@ -145,7 +145,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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@ -155,7 +156,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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VIRT_CLOCK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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@ -47,4 +47,8 @@ enum {
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SIFIVE_TIME_BASE = 0xBFF8
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SIFIVE_TIME_BASE = 0xBFF8
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};
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};
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enum {
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SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
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};
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#endif
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#endif
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@ -50,6 +50,10 @@ enum {
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SIFIVE_U_UART1_IRQ = 4
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SIFIVE_U_UART1_IRQ = 4
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};
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};
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enum {
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SIFIVE_U_CLOCK_FREQ = 1000000000
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};
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#define SIFIVE_U_PLIC_HART_CONFIG "MS"
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#define SIFIVE_U_PLIC_HART_CONFIG "MS"
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#define SIFIVE_U_PLIC_NUM_SOURCES 127
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#define SIFIVE_U_PLIC_NUM_SOURCES 127
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#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
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@ -42,6 +42,10 @@ enum {
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SPIKE_DRAM
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SPIKE_DRAM
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};
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};
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enum {
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SPIKE_CLOCK_FREQ = 1000000000
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};
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#if defined(TARGET_RISCV32)
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#if defined(TARGET_RISCV32)
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#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
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#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
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VIRTIO_NDEV = 10
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VIRTIO_NDEV = 10
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};
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};
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enum {
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VIRT_CLOCK_FREQ = 1000000000
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};
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#define VIRT_PLIC_HART_CONFIG "MS"
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#define VIRT_PLIC_HART_CONFIG "MS"
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#define VIRT_PLIC_NUM_SOURCES 127
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#define VIRT_PLIC_NUM_SOURCES 127
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#define VIRT_PLIC_NUM_PRIORITIES 7
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#define VIRT_PLIC_NUM_PRIORITIES 7
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