Merge remote-tracking branch 'origin/master' into staging
* origin/master:
mips: revert commit b332d24a8e
tcg/mips: fix invalid op definition errors
Necessary because patches got pushed by Aurelien before I pushed
the -rc2 tag.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
commit
2aa09da823
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@ -44,6 +44,7 @@
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#include "sysemu/blockdev.h"
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#include "sysemu/blockdev.h"
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#include "exec/address-spaces.h"
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#include "exec/address-spaces.h"
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#include "sysemu/qtest.h"
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#include "sysemu/qtest.h"
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#include "qemu/error-report.h"
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#define DEBUG_FULONG2E_INIT
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#define DEBUG_FULONG2E_INIT
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@ -335,7 +336,8 @@ static void mips_fulong2e_init(QEMUMachineInitArgs *args)
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if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
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if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
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!kernel_filename && !qtest_enabled()) {
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!kernel_filename && !qtest_enabled()) {
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fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", bios_name);
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error_report("Could not load MIPS bios '%s'", bios_name);
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exit(1);
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}
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}
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}
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}
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@ -43,6 +43,7 @@
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "exec/address-spaces.h"
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#include "exec/address-spaces.h"
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#include "sysemu/qtest.h"
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#include "sysemu/qtest.h"
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#include "qemu/error-report.h"
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enum jazz_model_e
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enum jazz_model_e
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{
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{
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@ -178,8 +179,8 @@ static void mips_jazz_init(MemoryRegion *address_space,
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bios_size = -1;
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bios_size = -1;
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}
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}
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if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
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if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
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fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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error_report("Could not load MIPS bios '%s'", bios_name);
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bios_name);
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exit(1);
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}
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}
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/* Init CPU internal devices */
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/* Init CPU internal devices */
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@ -49,6 +49,7 @@
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#include "hw/sysbus.h" /* SysBusDevice */
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#include "hw/sysbus.h" /* SysBusDevice */
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#include "qemu/host-utils.h"
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#include "qemu/host-utils.h"
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#include "sysemu/qtest.h"
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#include "sysemu/qtest.h"
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#include "qemu/error-report.h"
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//#define DEBUG_BOARD_INIT
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//#define DEBUG_BOARD_INIT
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@ -1008,9 +1009,9 @@ void mips_malta_init(QEMUMachineInitArgs *args)
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}
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}
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if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
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if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
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!kernel_filename && !qtest_enabled()) {
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!kernel_filename && !qtest_enabled()) {
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fprintf(stderr,
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error_report("Could not load MIPS bios '%s', and no "
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"qemu: Warning, could not load MIPS bios '%s', and no -kernel argument was specified\n",
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"-kernel argument was specified", bios_name);
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bios_name);
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exit(1);
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}
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}
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}
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}
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/* In little endian mode the 32bit words in the bios are swapped,
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/* In little endian mode the 32bit words in the bios are swapped,
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@ -37,6 +37,7 @@
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#include "elf.h"
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#include "elf.h"
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "exec/address-spaces.h"
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#include "exec/address-spaces.h"
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#include "qemu/error-report.h"
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static struct _loaderparams {
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static struct _loaderparams {
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int ram_size;
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int ram_size;
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@ -191,9 +192,9 @@ mips_mipssim_init(QEMUMachineInitArgs *args)
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}
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}
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if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
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if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
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/* Bail out if we have neither a kernel image nor boot vector code. */
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/* Bail out if we have neither a kernel image nor boot vector code. */
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fprintf(stderr,
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error_report("Could not load MIPS bios '%s', and no "
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"qemu: Warning, could not load MIPS bios '%s', and no -kernel argument was specified\n",
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"-kernel argument was specified", filename);
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filename);
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exit(1);
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} else {
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} else {
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/* We have a boot vector start address. */
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/* We have a boot vector start address. */
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env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
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env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
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@ -1617,19 +1617,29 @@ static const TCGTargetOpDef mips_op_defs[] = {
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{ INDEX_op_shl_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_shl_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_shr_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_shr_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_sar_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_sar_i32, { "r", "rZ", "ri" } },
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#if TCG_TARGET_HAS_rot_i32
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{ INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
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#endif
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#if TCG_TARGET_HAS_bswap16_i32
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{ INDEX_op_bswap16_i32, { "r", "r" } },
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{ INDEX_op_bswap16_i32, { "r", "r" } },
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#endif
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#if TCG_TARGET_HAS_bswap32_i32
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{ INDEX_op_bswap32_i32, { "r", "r" } },
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{ INDEX_op_bswap32_i32, { "r", "r" } },
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#endif
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{ INDEX_op_ext8s_i32, { "r", "rZ" } },
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{ INDEX_op_ext8s_i32, { "r", "rZ" } },
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{ INDEX_op_ext16s_i32, { "r", "rZ" } },
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{ INDEX_op_ext16s_i32, { "r", "rZ" } },
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#if TCG_TARGET_HAS_deposit_i32
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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#endif
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{ INDEX_op_brcond_i32, { "rZ", "rZ" } },
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{ INDEX_op_brcond_i32, { "rZ", "rZ" } },
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#if TCG_TARGET_HAS_movcond_i32
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{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
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{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
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#endif
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{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
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{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
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