target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline
Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally aligned memory accesses for load/store instructions. Signed-off-by: Julia Suvorova <jusual@mail.ru> Message-id: 20180622080138.17702-3-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1100,7 +1100,14 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)
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static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, TCGMemOp opc)
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int index, TCGMemOp opc)
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{
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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TCGv addr;
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if (arm_dc_feature(s, ARM_FEATURE_M) &&
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!arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
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opc |= MO_ALIGN;
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}
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addr = gen_aa32_addr(s, a32, opc);
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tcg_gen_qemu_ld_i32(val, addr, index, opc);
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tcg_gen_qemu_ld_i32(val, addr, index, opc);
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tcg_temp_free(addr);
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tcg_temp_free(addr);
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}
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}
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@ -1108,7 +1115,14 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, TCGMemOp opc)
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int index, TCGMemOp opc)
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{
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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TCGv addr;
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if (arm_dc_feature(s, ARM_FEATURE_M) &&
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!arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
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opc |= MO_ALIGN;
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}
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addr = gen_aa32_addr(s, a32, opc);
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tcg_gen_qemu_st_i32(val, addr, index, opc);
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tcg_gen_qemu_st_i32(val, addr, index, opc);
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tcg_temp_free(addr);
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tcg_temp_free(addr);
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}
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}
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