hw/display/cirrus_vga: Use qemu_log_mask(ERROR) instead of debug printf
Replace some debug printf() calls by qemu_log_mask(LOG_GUEST_ERROR). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200526062252.19852-6-f4bug@amsat.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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@ -978,9 +978,8 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
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s->cirrus_blt_pixelwidth = 4;
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break;
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default:
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#ifdef DEBUG_BITBLT
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printf("cirrus: bitblt - pixel width is unknown\n");
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: bitblt - pixel width is unknown\n");
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goto bitblt_ignore;
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}
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s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
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@ -1037,7 +1036,9 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
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} else {
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
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if (s->cirrus_blt_pixelwidth > 2) {
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printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: src transparent without colorexpand "
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"must be 8bpp or 16bpp\n");
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goto bitblt_ignore;
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}
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
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@ -1135,10 +1136,9 @@ static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
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ret = 16;
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break; /* XGA HiColor */
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: invalid DAC value %x in 16bpp\n",
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(s->cirrus_hidden_dac_data & 0xf));
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: invalid DAC value 0x%x in 16bpp\n",
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(s->cirrus_hidden_dac_data & 0xf));
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ret = 15; /* XXX */
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break;
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}
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@ -1307,11 +1307,9 @@ static int cirrus_vga_read_sr(CirrusVGAState * s)
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#endif
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return s->vga.sr[s->vga.sr_index];
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: inport sr_index 0x%02x\n", s->vga.sr_index);
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return 0xff;
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break;
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}
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}
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@ -1400,10 +1398,9 @@ static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
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cirrus_update_memory_access(s);
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break;
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: outport sr_index %02x, sr_value %02x\n",
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s->vga.sr_index, val);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
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s->vga.sr_index, val);
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break;
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}
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}
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@ -1501,9 +1498,8 @@ static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
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if (reg_index < 0x3a) {
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return s->vga.gr[reg_index];
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} else {
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#ifdef DEBUG_CIRRUS
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printf("cirrus: inport gr_index %02x\n", reg_index);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: inport gr_index 0x%02x\n", reg_index);
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return 0xff;
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}
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}
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@ -1590,10 +1586,9 @@ cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
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cirrus_write_bitblt(s, reg_value);
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break;
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
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reg_value);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: outport gr_index 0x%02x, gr_value 0x%02x\n",
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reg_index, reg_value);
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break;
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}
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}
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@ -1648,9 +1643,8 @@ static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
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return s->vga.ar_index & 0x3f;
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break;
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: inport cr_index %02x\n", reg_index);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: inport cr_index 0x%02x\n", reg_index);
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return 0xff;
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}
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}
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@ -1721,10 +1715,9 @@ static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
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break;
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case 0x25: // Part Status
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: outport cr_index %02x, cr_value %02x\n",
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s->vga.cr_index, reg_value);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: outport cr_index 0x%02x, cr_value 0x%02x\n",
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s->vga.cr_index, reg_value);
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break;
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}
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}
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@ -1834,9 +1827,8 @@ static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
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value = cirrus_vga_read_gr(s, 0x31);
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break;
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: mmio read - address 0x%04x\n", address);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: mmio read - address 0x%04x\n", address);
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break;
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}
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@ -1946,10 +1938,9 @@ static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
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cirrus_vga_write_gr(s, 0x31, value);
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break;
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
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address, value);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
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address, value);
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break;
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}
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}
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@ -2047,9 +2038,8 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
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}
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} else {
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val = 0xff;
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#ifdef DEBUG_CIRRUS
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printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr);
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}
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return val;
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}
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@ -2112,10 +2102,9 @@ static void cirrus_vga_mem_write(void *opaque,
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cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
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}
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} else {
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#ifdef DEBUG_CIRRUS
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printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
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mem_value);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: mem_writeb 0x" TARGET_FMT_plx " "
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"value 0x%02" PRIu64 "\n", addr, mem_value);
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}
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}
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