sparc64: unbreak
... by making apb a subclass of TYPE_PCI_HOST_BRIDGE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-21-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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@ -70,9 +70,14 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#define MAX_IVEC 0x40
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#define MAX_IVEC 0x40
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#define NO_IRQ_REQUEST (MAX_IVEC + 1)
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#define NO_IRQ_REQUEST (MAX_IVEC + 1)
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#define TYPE_APB "pbm"
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#define APB_DEVICE(obj) \
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OBJECT_CHECK(APBState, (obj), TYPE_APB)
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typedef struct APBState {
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typedef struct APBState {
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SysBusDevice busdev;
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PCIHostState parent_obj;
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PCIBus *bus;
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MemoryRegion apb_config;
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MemoryRegion apb_config;
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MemoryRegion pci_config;
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MemoryRegion pci_config;
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MemoryRegion pci_mmio;
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MemoryRegion pci_mmio;
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@ -284,10 +289,11 @@ static void apb_pci_config_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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uint64_t val, unsigned size)
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{
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{
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APBState *s = opaque;
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APBState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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val = qemu_bswap_len(val, size);
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val = qemu_bswap_len(val, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
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pci_data_write(s->bus, addr, val, size);
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pci_data_write(phb->bus, addr, val, size);
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}
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}
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static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
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static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
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@ -295,8 +301,9 @@ static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
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{
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{
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uint32_t ret;
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uint32_t ret;
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APBState *s = opaque;
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APBState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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ret = pci_data_read(s->bus, addr, size);
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ret = pci_data_read(phb->bus, addr, size);
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ret = qemu_bswap_len(ret, size);
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ret = qemu_bswap_len(ret, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
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return ret;
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return ret;
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@ -381,12 +388,13 @@ PCIBus *pci_apb_init(hwaddr special_base,
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{
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{
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DeviceState *dev;
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DeviceState *dev;
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SysBusDevice *s;
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SysBusDevice *s;
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PCIHostState *phb;
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APBState *d;
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APBState *d;
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PCIDevice *pci_dev;
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PCIDevice *pci_dev;
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PCIBridge *br;
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PCIBridge *br;
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/* Ultrasparc PBM main bus */
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/* Ultrasparc PBM main bus */
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dev = qdev_create(NULL, "pbm");
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dev = qdev_create(NULL, TYPE_APB);
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qdev_init_nofail(dev);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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s = SYS_BUS_DEVICE(dev);
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/* apb_config */
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/* apb_config */
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@ -395,12 +403,13 @@ PCIBus *pci_apb_init(hwaddr special_base,
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sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
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sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
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/* pci_ioport */
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/* pci_ioport */
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sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
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sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
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d = FROM_SYSBUS(APBState, s);
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d = APB_DEVICE(dev);
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memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
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memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
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memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
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memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
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d->bus = pci_register_bus(&d->busdev.qdev, "pci",
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phb = PCI_HOST_BRIDGE(dev);
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phb->bus = pci_register_bus(DEVICE(phb), "pci",
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pci_apb_set_irq, pci_pbm_map_irq, d,
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pci_apb_set_irq, pci_pbm_map_irq, d,
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&d->pci_mmio,
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&d->pci_mmio,
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get_system_io(),
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get_system_io(),
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@ -409,10 +418,10 @@ PCIBus *pci_apb_init(hwaddr special_base,
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*pbm_irqs = d->pbm_irqs;
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*pbm_irqs = d->pbm_irqs;
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d->ivec_irqs = ivec_irqs;
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d->ivec_irqs = ivec_irqs;
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pci_create_simple(d->bus, 0, "pbm-pci");
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pci_create_simple(phb->bus, 0, "pbm-pci");
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/* APB secondary busses */
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/* APB secondary busses */
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pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
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"pbm-bridge");
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"pbm-bridge");
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br = DO_UPCAST(PCIBridge, dev, pci_dev);
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br = DO_UPCAST(PCIBridge, dev, pci_dev);
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pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
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pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
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@ -420,7 +429,7 @@ PCIBus *pci_apb_init(hwaddr special_base,
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qdev_init_nofail(&pci_dev->qdev);
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qdev_init_nofail(&pci_dev->qdev);
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*bus2 = pci_bridge_get_sec_bus(br);
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*bus2 = pci_bridge_get_sec_bus(br);
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pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
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"pbm-bridge");
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"pbm-bridge");
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br = DO_UPCAST(PCIBridge, dev, pci_dev);
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br = DO_UPCAST(PCIBridge, dev, pci_dev);
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pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
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pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
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@ -428,13 +437,13 @@ PCIBus *pci_apb_init(hwaddr special_base,
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qdev_init_nofail(&pci_dev->qdev);
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qdev_init_nofail(&pci_dev->qdev);
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*bus3 = pci_bridge_get_sec_bus(br);
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*bus3 = pci_bridge_get_sec_bus(br);
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return d->bus;
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return phb->bus;
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}
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}
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static void pci_pbm_reset(DeviceState *d)
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static void pci_pbm_reset(DeviceState *d)
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{
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{
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unsigned int i;
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unsigned int i;
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APBState *s = container_of(d, APBState, busdev.qdev);
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APBState *s = APB_DEVICE(d);
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for (i = 0; i < 8; i++) {
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
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@ -463,7 +472,7 @@ static int pci_pbm_init_device(SysBusDevice *dev)
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APBState *s;
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APBState *s;
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unsigned int i;
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unsigned int i;
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s = FROM_SYSBUS(APBState, dev);
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s = APB_DEVICE(dev);
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for (i = 0; i < 8; i++) {
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
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s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
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}
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}
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@ -531,8 +540,8 @@ static void pbm_host_class_init(ObjectClass *klass, void *data)
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}
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}
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static const TypeInfo pbm_host_info = {
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static const TypeInfo pbm_host_info = {
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.name = "pbm",
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.name = TYPE_APB,
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.parent = TYPE_SYS_BUS_DEVICE,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(APBState),
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.instance_size = sizeof(APBState),
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.class_init = pbm_host_class_init,
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.class_init = pbm_host_class_init,
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};
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};
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