hw/sd/aspeed_sdhci: New device
The Aspeed SOCs have two SD/MMC controllers. Add a device that encapsulates both of these controllers and models the Aspeed-specific registers and behavior. Tested by reading from mmcblk0 in Linux: qemu-system-arm -machine romulus-bmc -nographic \ -drive file=flash-romulus,format=raw,if=mtd \ -device sd-card,drive=sd0 -drive file=_tmp/kernel,format=raw,if=sd,id=sd0 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190925143248.10000-3-clg@kaod.org [clg: - changed the controller MMIO window size to 0x1000 - moved the MMIO mapping of the SDHCI slots at the SoC level - merged code to add SD drives on the SD buses at the machine level ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
1ff68783f6
commit
2bea128c3d
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@ -170,6 +170,7 @@ static void aspeed_board_init(MachineState *machine,
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AspeedSoCClass *sc;
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AspeedSoCClass *sc;
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DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
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DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
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ram_addr_t max_ram_size;
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ram_addr_t max_ram_size;
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int i;
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bmc = g_new0(AspeedBoardState, 1);
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bmc = g_new0(AspeedBoardState, 1);
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@ -252,6 +253,19 @@ static void aspeed_board_init(MachineState *machine,
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cfg->i2c_init(bmc);
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cfg->i2c_init(bmc);
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}
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}
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for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) {
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SDHCIState *sdhci = &bmc->soc.sdhci.slots[i];
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DriveInfo *dinfo = drive_get_next(IF_SD);
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BlockBackend *blk;
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DeviceState *card;
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blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
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card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
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TYPE_SD_CARD);
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qdev_prop_set_drive(card, "drive", blk, &error_fatal);
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object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
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}
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arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
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arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
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}
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}
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@ -373,7 +387,6 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
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mc->desc = board->desc;
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mc->desc = board->desc;
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mc->init = aspeed_machine_init;
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mc->init = aspeed_machine_init;
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mc->max_cpus = ASPEED_CPUS_NUM;
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mc->max_cpus = ASPEED_CPUS_NUM;
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mc->no_sdcard = 1;
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mc->no_floppy = 1;
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mc->no_floppy = 1;
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mc->no_cdrom = 1;
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mc->no_cdrom = 1;
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mc->no_parallel = 1;
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mc->no_parallel = 1;
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@ -36,6 +36,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
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[ASPEED_XDMA] = 0x1E6E7000,
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[ASPEED_XDMA] = 0x1E6E7000,
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[ASPEED_ADC] = 0x1E6E9000,
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[ASPEED_ADC] = 0x1E6E9000,
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[ASPEED_SRAM] = 0x1E720000,
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[ASPEED_SRAM] = 0x1E720000,
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[ASPEED_SDHCI] = 0x1E740000,
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[ASPEED_GPIO] = 0x1E780000,
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[ASPEED_GPIO] = 0x1E780000,
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[ASPEED_RTC] = 0x1E781000,
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[ASPEED_RTC] = 0x1E781000,
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[ASPEED_TIMER1] = 0x1E782000,
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[ASPEED_TIMER1] = 0x1E782000,
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@ -63,6 +64,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
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[ASPEED_XDMA] = 0x1E6E7000,
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[ASPEED_XDMA] = 0x1E6E7000,
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[ASPEED_ADC] = 0x1E6E9000,
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[ASPEED_ADC] = 0x1E6E9000,
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[ASPEED_SRAM] = 0x1E720000,
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[ASPEED_SRAM] = 0x1E720000,
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[ASPEED_SDHCI] = 0x1E740000,
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[ASPEED_GPIO] = 0x1E780000,
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[ASPEED_GPIO] = 0x1E780000,
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[ASPEED_RTC] = 0x1E781000,
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[ASPEED_RTC] = 0x1E781000,
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[ASPEED_TIMER1] = 0x1E782000,
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[ASPEED_TIMER1] = 0x1E782000,
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@ -108,6 +110,7 @@ static const int aspeed_soc_ast2400_irqmap[] = {
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[ASPEED_ETH1] = 2,
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[ASPEED_ETH1] = 2,
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[ASPEED_ETH2] = 3,
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[ASPEED_ETH2] = 3,
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[ASPEED_XDMA] = 6,
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[ASPEED_XDMA] = 6,
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[ASPEED_SDHCI] = 26,
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};
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};
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#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
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#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
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@ -230,6 +233,15 @@ static void aspeed_soc_init(Object *obj)
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
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sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
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typename);
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typename);
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sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
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TYPE_ASPEED_SDHCI);
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/* Init sd card slot class here so that they're under the correct parent */
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for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
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sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
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sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
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}
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}
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}
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static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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@ -419,6 +431,17 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
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aspeed_soc_get_irq(s, ASPEED_GPIO));
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aspeed_soc_get_irq(s, ASPEED_GPIO));
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/* SDHCI */
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object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
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sc->info->memmap[ASPEED_SDHCI]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
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aspeed_soc_get_irq(s, ASPEED_SDHCI));
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}
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}
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static Property aspeed_soc_properties[] = {
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static Property aspeed_soc_properties[] = {
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DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
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DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
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@ -8,3 +8,4 @@ obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o
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obj-$(CONFIG_OMAP) += omap_mmc.o
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obj-$(CONFIG_OMAP) += omap_mmc.o
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obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
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obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
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obj-$(CONFIG_RASPI) += bcm2835_sdhost.o
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obj-$(CONFIG_RASPI) += bcm2835_sdhost.o
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obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o
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198
hw/sd/aspeed_sdhci.c
Normal file
198
hw/sd/aspeed_sdhci.c
Normal file
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@ -0,0 +1,198 @@
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/*
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* Aspeed SD Host Controller
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* Eddie James <eajames@linux.ibm.com>
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*
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* Copyright (C) 2019 IBM Corp
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* SPDX-License-Identifer: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/sd/aspeed_sdhci.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#define ASPEED_SDHCI_INFO 0x00
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#define ASPEED_SDHCI_INFO_RESET 0x00030000
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#define ASPEED_SDHCI_DEBOUNCE 0x04
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#define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
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#define ASPEED_SDHCI_BUS 0x08
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#define ASPEED_SDHCI_SDIO_140 0x10
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#define ASPEED_SDHCI_SDIO_148 0x18
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#define ASPEED_SDHCI_SDIO_240 0x20
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#define ASPEED_SDHCI_SDIO_248 0x28
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#define ASPEED_SDHCI_WP_POL 0xec
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#define ASPEED_SDHCI_CARD_DET 0xf0
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#define ASPEED_SDHCI_IRQ_STAT 0xfc
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#define TO_REG(addr) ((addr) / sizeof(uint32_t))
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static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
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{
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uint32_t val = 0;
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AspeedSDHCIState *sdhci = opaque;
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switch (addr) {
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case ASPEED_SDHCI_SDIO_140:
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val = (uint32_t)sdhci->slots[0].capareg;
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break;
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case ASPEED_SDHCI_SDIO_148:
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val = (uint32_t)sdhci->slots[0].maxcurr;
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break;
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case ASPEED_SDHCI_SDIO_240:
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val = (uint32_t)sdhci->slots[1].capareg;
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break;
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case ASPEED_SDHCI_SDIO_248:
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val = (uint32_t)sdhci->slots[1].maxcurr;
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break;
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default:
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if (addr < ASPEED_SDHCI_REG_SIZE) {
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val = sdhci->regs[TO_REG(addr)];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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}
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}
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return (uint64_t)val;
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}
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static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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AspeedSDHCIState *sdhci = opaque;
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switch (addr) {
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case ASPEED_SDHCI_SDIO_140:
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sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;
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break;
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case ASPEED_SDHCI_SDIO_148:
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sdhci->slots[0].maxcurr = (uint64_t)(uint32_t)val;
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break;
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case ASPEED_SDHCI_SDIO_240:
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sdhci->slots[1].capareg = (uint64_t)(uint32_t)val;
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break;
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case ASPEED_SDHCI_SDIO_248:
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sdhci->slots[1].maxcurr = (uint64_t)(uint32_t)val;
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break;
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default:
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if (addr < ASPEED_SDHCI_REG_SIZE) {
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sdhci->regs[TO_REG(addr)] = (uint32_t)val;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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}
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}
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}
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static const MemoryRegionOps aspeed_sdhci_ops = {
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.read = aspeed_sdhci_read,
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.write = aspeed_sdhci_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void aspeed_sdhci_set_irq(void *opaque, int n, int level)
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{
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AspeedSDHCIState *sdhci = opaque;
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if (level) {
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sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n);
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qemu_irq_raise(sdhci->irq);
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} else {
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sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n);
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qemu_irq_lower(sdhci->irq);
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}
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}
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static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
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{
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Error *err = NULL;
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
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/* Create input irqs for the slots */
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qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
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sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS);
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sysbus_init_irq(sbd, &sdhci->irq);
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memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,
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sdhci, TYPE_ASPEED_SDHCI, 0x1000);
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sysbus_init_mmio(sbd, &sdhci->iomem);
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for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
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Object *sdhci_slot = OBJECT(&sdhci->slots[i]);
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SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);
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object_property_set_int(sdhci_slot, 2, "sd-spec-version", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_uint(sdhci_slot, ASPEED_SDHCI_CAPABILITIES,
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"capareg", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(sdhci_slot, true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i));
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memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100,
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&sdhci->slots[i].iomem);
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}
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}
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static void aspeed_sdhci_reset(DeviceState *dev)
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{
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AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
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memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);
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sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_RESET;
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sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;
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}
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static const VMStateDescription vmstate_aspeed_sdhci = {
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.name = TYPE_ASPEED_SDHCI,
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(classp);
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dc->realize = aspeed_sdhci_realize;
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dc->reset = aspeed_sdhci_reset;
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dc->vmsd = &vmstate_aspeed_sdhci;
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}
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|
static TypeInfo aspeed_sdhci_info = {
|
||||||
|
.name = TYPE_ASPEED_SDHCI,
|
||||||
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||||||
|
.instance_size = sizeof(AspeedSDHCIState),
|
||||||
|
.class_init = aspeed_sdhci_class_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void aspeed_sdhci_register_types(void)
|
||||||
|
{
|
||||||
|
type_register_static(&aspeed_sdhci_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(aspeed_sdhci_register_types)
|
|
@ -24,6 +24,7 @@
|
||||||
#include "hw/net/ftgmac100.h"
|
#include "hw/net/ftgmac100.h"
|
||||||
#include "target/arm/cpu.h"
|
#include "target/arm/cpu.h"
|
||||||
#include "hw/gpio/aspeed_gpio.h"
|
#include "hw/gpio/aspeed_gpio.h"
|
||||||
|
#include "hw/sd/aspeed_sdhci.h"
|
||||||
|
|
||||||
#define ASPEED_SPIS_NUM 2
|
#define ASPEED_SPIS_NUM 2
|
||||||
#define ASPEED_WDTS_NUM 3
|
#define ASPEED_WDTS_NUM 3
|
||||||
|
@ -50,6 +51,7 @@ typedef struct AspeedSoCState {
|
||||||
AspeedWDTState wdt[ASPEED_WDTS_NUM];
|
AspeedWDTState wdt[ASPEED_WDTS_NUM];
|
||||||
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
|
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
|
||||||
AspeedGPIOState gpio;
|
AspeedGPIOState gpio;
|
||||||
|
AspeedSDHCIState sdhci;
|
||||||
} AspeedSoCState;
|
} AspeedSoCState;
|
||||||
|
|
||||||
#define TYPE_ASPEED_SOC "aspeed-soc"
|
#define TYPE_ASPEED_SOC "aspeed-soc"
|
||||||
|
@ -93,6 +95,7 @@ enum {
|
||||||
ASPEED_SCU,
|
ASPEED_SCU,
|
||||||
ASPEED_ADC,
|
ASPEED_ADC,
|
||||||
ASPEED_SRAM,
|
ASPEED_SRAM,
|
||||||
|
ASPEED_SDHCI,
|
||||||
ASPEED_GPIO,
|
ASPEED_GPIO,
|
||||||
ASPEED_RTC,
|
ASPEED_RTC,
|
||||||
ASPEED_TIMER1,
|
ASPEED_TIMER1,
|
||||||
|
|
34
include/hw/sd/aspeed_sdhci.h
Normal file
34
include/hw/sd/aspeed_sdhci.h
Normal file
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
* Aspeed SD Host Controller
|
||||||
|
* Eddie James <eajames@linux.ibm.com>
|
||||||
|
*
|
||||||
|
* Copyright (C) 2019 IBM Corp
|
||||||
|
* SPDX-License-Identifer: GPL-2.0-or-later
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ASPEED_SDHCI_H
|
||||||
|
#define ASPEED_SDHCI_H
|
||||||
|
|
||||||
|
#include "hw/sd/sdhci.h"
|
||||||
|
|
||||||
|
#define TYPE_ASPEED_SDHCI "aspeed.sdhci"
|
||||||
|
#define ASPEED_SDHCI(obj) OBJECT_CHECK(AspeedSDHCIState, (obj), \
|
||||||
|
TYPE_ASPEED_SDHCI)
|
||||||
|
|
||||||
|
#define ASPEED_SDHCI_CAPABILITIES 0x01E80080
|
||||||
|
#define ASPEED_SDHCI_NUM_SLOTS 2
|
||||||
|
#define ASPEED_SDHCI_NUM_REGS (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t))
|
||||||
|
#define ASPEED_SDHCI_REG_SIZE 0x100
|
||||||
|
|
||||||
|
typedef struct AspeedSDHCIState {
|
||||||
|
SysBusDevice parent;
|
||||||
|
|
||||||
|
SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS];
|
||||||
|
|
||||||
|
MemoryRegion iomem;
|
||||||
|
qemu_irq irq;
|
||||||
|
|
||||||
|
uint32_t regs[ASPEED_SDHCI_NUM_REGS];
|
||||||
|
} AspeedSDHCIState;
|
||||||
|
|
||||||
|
#endif /* ASPEED_SDHCI_H */
|
Loading…
Reference in a new issue