target-mips: apply CP0.PageMask before writing into TLB entry
PFN0 and PFN1 have to be masked out with PageMask_Mask. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [Yongbok Kim: Added commit message] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
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@ -2008,6 +2008,7 @@ static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
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static void r4k_fill_tlb(CPUMIPSState *env, int idx)
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{
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r4k_tlb_t *tlb;
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uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
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/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
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tlb = &env->tlb->mmu.r4k.tlb[idx];
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@ -2028,13 +2029,13 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx)
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tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
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tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
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tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
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tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
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tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
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tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
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tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
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tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
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tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
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tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
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tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
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tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
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}
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void r4k_helper_tlbinv(CPUMIPSState *env)
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