target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
Will be used for SVE2 isa subset enablement. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -947,6 +947,7 @@ struct ARMCPU {
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uint64_t id_aa64mmfr2;
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uint64_t id_aa64mmfr2;
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uint64_t id_aa64dfr0;
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uint64_t id_aa64dfr0;
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uint64_t id_aa64dfr1;
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uint64_t id_aa64dfr1;
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uint64_t id_aa64zfr0;
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} isar;
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} isar;
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uint64_t midr;
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uint64_t midr;
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uint32_t revidr;
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uint32_t revidr;
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@ -2034,6 +2035,16 @@ FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
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FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
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FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
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FIELD(ID_AA64DFR0, MTPMU, 48, 4)
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FIELD(ID_AA64DFR0, MTPMU, 48, 4)
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FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
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FIELD(ID_AA64ZFR0, AES, 4, 4)
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FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
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FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
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FIELD(ID_AA64ZFR0, SHA3, 32, 4)
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FIELD(ID_AA64ZFR0, SM4, 40, 4)
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FIELD(ID_AA64ZFR0, I8MM, 44, 4)
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FIELD(ID_AA64ZFR0, F32MM, 52, 4)
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FIELD(ID_AA64ZFR0, F64MM, 56, 4)
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FIELD(ID_DFR0, COPDBG, 0, 4)
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FIELD(ID_DFR0, COPDBG, 0, 4)
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FIELD(ID_DFR0, COPSDBG, 4, 4)
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FIELD(ID_DFR0, COPSDBG, 4, 4)
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FIELD(ID_DFR0, MMAPDBG, 8, 4)
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FIELD(ID_DFR0, MMAPDBG, 8, 4)
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@ -4225,6 +4236,11 @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
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}
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}
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static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
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}
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/*
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
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*/
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@ -7879,8 +7879,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
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.access = PL1_R, .type = ARM_CP_CONST,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa64_tid3,
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.accessfn = access_aa64_tid3,
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/* At present, only SVEver == 0 is defined anyway. */
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.resetvalue = cpu->isar.id_aa64zfr0 },
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.resetvalue = 0 },
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{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
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.access = PL1_R, .type = ARM_CP_CONST,
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.access = PL1_R, .type = ARM_CP_CONST,
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@ -647,17 +647,26 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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if (err < 0) {
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return false;
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}
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/* Add feature bits that can't appear until after VCPU init. */
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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if (sve_supported) {
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t = ahcf->isar.id_aa64pfr0;
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t = ahcf->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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ahcf->isar.id_aa64pfr0 = t;
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ahcf->isar.id_aa64pfr0 = t;
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/*
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* Before v5.1, KVM did not support SVE and did not expose
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* ID_AA64ZFR0_EL1 even as RAZ. After v5.1, KVM still does
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* not expose the register to "user" requests like this
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* unless the host supports SVE.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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if (err < 0) {
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return false;
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}
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}
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/*
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/*
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