target-ppc: Fix rlwimi, rlwinm, rlwnm
In 63ae0915f8
, I arranged to use a 32-bit rotate, without
considering the effect of a mask value that wraps around to
the high bits of the word.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
parent
d917e88d85
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2e11b15dff
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@ -1636,7 +1636,6 @@ static void gen_rlwimi(DisasContext *ctx)
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tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
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} else {
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target_ulong mask;
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TCGv_i32 t0;
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TCGv t1;
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#if defined(TARGET_PPC64)
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@ -1645,12 +1644,21 @@ static void gen_rlwimi(DisasContext *ctx)
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#endif
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mask = MASK(mb, me);
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new();
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tcg_gen_trunc_tl_i32(t0, t_rs);
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tcg_gen_rotli_i32(t0, t0, sh);
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tcg_gen_extu_i32_tl(t1, t0);
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tcg_temp_free_i32(t0);
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if (mask <= 0xffffffffu) {
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TCGv_i32 t0 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, t_rs);
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tcg_gen_rotli_i32(t0, t0, sh);
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tcg_gen_extu_i32_tl(t1, t0);
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tcg_temp_free_i32(t0);
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} else {
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#if defined(TARGET_PPC64)
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tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
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tcg_gen_rotli_i64(t1, t1, sh);
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#else
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g_assert_not_reached();
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#endif
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}
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tcg_gen_andi_tl(t1, t1, mask);
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tcg_gen_andi_tl(t_ra, t_ra, ~mask);
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@ -1678,20 +1686,30 @@ static void gen_rlwinm(DisasContext *ctx)
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tcg_gen_ext32u_tl(t_ra, t_rs);
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tcg_gen_shri_tl(t_ra, t_ra, mb);
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} else {
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target_ulong mask;
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#if defined(TARGET_PPC64)
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mb += 32;
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me += 32;
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#endif
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if (sh == 0) {
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tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
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} else {
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TCGv_i32 t0 = tcg_temp_new_i32();
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mask = MASK(mb, me);
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if (sh == 0) {
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tcg_gen_andi_tl(t_ra, t_rs, mask);
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} else if (mask <= 0xffffffffu) {
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TCGv_i32 t0 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, t_rs);
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tcg_gen_rotli_i32(t0, t0, sh);
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tcg_gen_andi_i32(t0, t0, MASK(mb, me));
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tcg_gen_andi_i32(t0, t0, mask);
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tcg_gen_extu_i32_tl(t_ra, t0);
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tcg_temp_free_i32(t0);
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} else {
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#if defined(TARGET_PPC64)
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tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
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tcg_gen_rotli_i64(t_ra, t_ra, sh);
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tcg_gen_andi_i64(t_ra, t_ra, mask);
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#else
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g_assert_not_reached();
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#endif
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}
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}
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if (unlikely(Rc(ctx->opcode) != 0)) {
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@ -1707,24 +1725,37 @@ static void gen_rlwnm(DisasContext *ctx)
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TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
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uint32_t mb = MB(ctx->opcode);
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uint32_t me = ME(ctx->opcode);
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TCGv_i32 t0, t1;
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target_ulong mask;
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#if defined(TARGET_PPC64)
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mb += 32;
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me += 32;
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#endif
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mask = MASK(mb, me);
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, t_rb);
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tcg_gen_trunc_tl_i32(t1, t_rs);
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tcg_gen_andi_i32(t0, t0, 0x1f);
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tcg_gen_rotl_i32(t1, t1, t0);
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tcg_temp_free_i32(t0);
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if (mask <= 0xffffffffu) {
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, t_rb);
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tcg_gen_trunc_tl_i32(t1, t_rs);
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tcg_gen_andi_i32(t0, t0, 0x1f);
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tcg_gen_rotl_i32(t1, t1, t0);
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tcg_gen_extu_i32_tl(t_ra, t1);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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} else {
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#if defined(TARGET_PPC64)
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_andi_i64(t0, t_rb, 0x1f);
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tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
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tcg_gen_rotl_i64(t_ra, t_ra, t0);
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tcg_temp_free_i64(t0);
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#else
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g_assert_not_reached();
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#endif
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}
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tcg_gen_andi_i32(t1, t1, MASK(mb, me));
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tcg_gen_extu_i32_tl(t_ra, t1);
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tcg_temp_free_i32(t1);
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tcg_gen_andi_tl(t_ra, t_ra, mask);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, t_ra);
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