xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done
Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20171126231634.9531-12-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
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uint8_t addr_length;
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uint8_t addr_length;
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if (fifo8_is_empty(&s->tx_fifo)) {
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if (fifo8_is_empty(&s->tx_fifo)) {
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if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
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s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
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}
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xilinx_spips_update_ixr(s);
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xilinx_spips_update_ixr(s);
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return;
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return;
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} else if (s->snoop_state == SNOOP_STRIPING) {
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} else if (s->snoop_state == SNOOP_STRIPING) {
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@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
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ret = s->regs[addr] & IXR_ALL;
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ret = s->regs[addr] & IXR_ALL;
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s->regs[addr] = 0;
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s->regs[addr] = 0;
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DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
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DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
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xilinx_spips_update_ixr(s);
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return ret;
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return ret;
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case R_INTR_MASK:
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case R_INTR_MASK:
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mask = IXR_ALL;
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mask = IXR_ALL;
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