target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm categories; this completes the implementation of those two groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-19-git-send-email-peter.maydell@linaro.org
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@ -6224,6 +6224,82 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
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handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
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handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
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}
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}
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/* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
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static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
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bool is_q, bool is_u,
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int immh, int immb, int rn, int rd)
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{
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bool is_double = extract32(immh, 3, 1);
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int immhb = immh << 3 | immb;
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int fracbits = (is_double ? 128 : 64) - immhb;
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int pass;
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TCGv_ptr tcg_fpstatus;
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TCGv_i32 tcg_rmode, tcg_shift;
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if (!extract32(immh, 2, 2)) {
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unallocated_encoding(s);
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return;
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}
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if (!is_scalar && !is_q && is_double) {
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unallocated_encoding(s);
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return;
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}
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assert(!(is_scalar && is_q));
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tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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tcg_fpstatus = get_fpstatus_ptr();
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tcg_shift = tcg_const_i32(fracbits);
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if (is_double) {
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int maxpass = is_scalar ? 1 : is_q ? 2 : 1;
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for (pass = 0; pass < maxpass; pass++) {
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TCGv_i64 tcg_op = tcg_temp_new_i64();
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read_vec_element(s, tcg_op, rn, pass, MO_64);
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if (is_u) {
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gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
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}
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write_vec_element(s, tcg_op, rd, pass, MO_64);
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tcg_temp_free_i64(tcg_op);
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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} else {
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int maxpass = is_scalar ? 1 : is_q ? 4 : 2;
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for (pass = 0; pass < maxpass; pass++) {
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TCGv_i32 tcg_op = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
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if (is_u) {
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gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
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}
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if (is_scalar) {
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write_fp_sreg(s, rd, tcg_op);
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} else {
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write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
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}
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tcg_temp_free_i32(tcg_op);
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}
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if (!is_q && !is_scalar) {
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clear_vec_high(s, rd);
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}
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}
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tcg_temp_free_ptr(tcg_fpstatus);
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tcg_temp_free_i32(tcg_shift);
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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tcg_temp_free_i32(tcg_rmode);
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}
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/* C3.6.9 AdvSIMD scalar shift by immediate
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/* C3.6.9 AdvSIMD scalar shift by immediate
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* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
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* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
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* +-----+---+-------------+------+------+--------+---+------+------+
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* +-----+---+-------------+------+------+--------+---+------+------+
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@ -6291,7 +6367,7 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
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handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd);
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handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd);
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break;
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break;
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case 0x1f: /* FCVTZS, FCVTZU */
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case 0x1f: /* FCVTZS, FCVTZU */
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unsupported_encoding(s, insn);
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handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
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break;
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break;
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default:
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default:
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unallocated_encoding(s);
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unallocated_encoding(s);
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@ -7543,7 +7619,7 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
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handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd);
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handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd);
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break;
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break;
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case 0x1f: /* FCVTZS/ FCVTZU */
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case 0x1f: /* FCVTZS/ FCVTZU */
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unsupported_encoding(s, insn);
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handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd);
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return;
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return;
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default:
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default:
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unallocated_encoding(s);
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unallocated_encoding(s);
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