hw/mips/cps: create CPC block inside CPS
Create Cluster Power Controller and add a link to the CPC MemoryRegion in GCR. Guest can enable / map CPC to any physical address by writing to the memory-mapped GCR_CPC_BASE register. Set vp-start-reset property to 1 to allow only first VP to run from reset. Others are brought up by the guest via CPC memory-mapped registers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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1f93a6e4f3
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2edd5261ff
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@ -82,6 +82,21 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
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cpu = MIPS_CPU(first_cpu);
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env = &cpu->env;
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/* Cluster Power Controller */
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object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
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qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
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object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
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object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
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object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
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/* Global Configuration Registers */
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gcr_base = env->CP0_CMGCRBase << 4;
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@ -91,6 +106,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
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object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
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object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
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object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
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object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
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object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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@ -15,6 +15,25 @@
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "hw/misc/mips_cmgcr.h"
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#include "hw/misc/mips_cpc.h"
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static inline bool is_cpc_connected(MIPSGCRState *s)
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{
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return s->cpc_mr != NULL;
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}
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static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)
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{
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if (is_cpc_connected(gcr)) {
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gcr->cpc_base = val & GCR_CPC_BASE_MSK;
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memory_region_transaction_begin();
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memory_region_set_address(gcr->cpc_mr,
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gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK);
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memory_region_set_enabled(gcr->cpc_mr,
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gcr->cpc_base & GCR_CPC_BASE_CPCEN_MSK);
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memory_region_transaction_commit();
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}
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}
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/* Read GCR registers */
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static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
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@ -30,6 +49,10 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
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return gcr->gcr_base;
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case GCR_REV_OFS:
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return gcr->gcr_rev;
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case GCR_CPC_BASE_OFS:
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return gcr->cpc_base;
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case GCR_CPC_STATUS_OFS:
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return is_cpc_connected(gcr);
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case GCR_L2_CONFIG_OFS:
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/* L2 BYPASS */
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return GCR_L2_CONFIG_BYPASS_MSK;
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@ -51,7 +74,12 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
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/* Write GCR registers */
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static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
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{
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MIPSGCRState *gcr = (MIPSGCRState *)opaque;
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switch (addr) {
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case GCR_CPC_BASE_OFS:
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update_cpc_base(gcr, data);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx
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" 0x%" PRIx64 "\n", size, addr, data);
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@ -73,11 +101,34 @@ static void mips_gcr_init(Object *obj)
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSGCRState *s = MIPS_GCR(obj);
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object_property_add_link(obj, "cpc", TYPE_MEMORY_REGION,
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(Object **)&s->cpc_mr,
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qdev_prop_allow_set_link_before_realize,
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OBJ_PROP_LINK_UNREF_ON_RELEASE,
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&error_abort);
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memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s,
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"mips-gcr", GCR_ADDRSPACE_SZ);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void mips_gcr_reset(DeviceState *dev)
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{
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MIPSGCRState *s = MIPS_GCR(dev);
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update_cpc_base(s, 0);
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}
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static const VMStateDescription vmstate_mips_gcr = {
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.name = "mips-gcr",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(cpc_base, MIPSGCRState),
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VMSTATE_END_OF_LIST()
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},
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};
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static Property mips_gcr_properties[] = {
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DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
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DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
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@ -89,6 +140,8 @@ static void mips_gcr_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = mips_gcr_properties;
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dc->vmsd = &vmstate_mips_gcr;
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dc->reset = mips_gcr_reset;
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}
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static const TypeInfo mips_gcr_info = {
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@ -22,6 +22,7 @@
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#include "hw/sysbus.h"
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#include "hw/misc/mips_cmgcr.h"
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#include "hw/misc/mips_cpc.h"
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#define TYPE_MIPS_CPS "mips-cps"
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#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
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@ -35,6 +36,7 @@ typedef struct MIPSCPSState {
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MemoryRegion container;
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MIPSGCRState gcr;
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MIPSCPCState cpc;
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} MIPSCPSState;
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qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
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@ -26,6 +26,8 @@
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#define GCR_CONFIG_OFS 0x0000
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#define GCR_BASE_OFS 0x0008
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#define GCR_REV_OFS 0x0030
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#define GCR_CPC_BASE_OFS 0x0088
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#define GCR_CPC_STATUS_OFS 0x00F0
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#define GCR_L2_CONFIG_OFS 0x0130
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/* Core Local and Core Other Block Register Map */
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@ -36,6 +38,11 @@
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#define GCR_L2_CONFIG_BYPASS_SHF 20
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#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
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/* GCR_CPC_BASE register fields */
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#define GCR_CPC_BASE_CPCEN_MSK 1
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#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
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#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
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typedef struct MIPSGCRState MIPSGCRState;
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struct MIPSGCRState {
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SysBusDevice parent_obj;
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@ -44,6 +51,9 @@ struct MIPSGCRState {
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int32_t num_vps;
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hwaddr gcr_base;
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MemoryRegion iomem;
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MemoryRegion *cpc_mr;
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uint64_t cpc_base;
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};
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#endif /* _MIPS_GCR_H */
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