qemu-sparc queue
-----BEGIN PGP SIGNATURE----- iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAl/1okYeHG1hcmsuY2F2 ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfSQwIAIIRv+KAfOna0Vbo K3I6ktJQYD+cCeG92NWHRYf/ojMl+wDHQjjM9CC5qJL20WIRKi90WXNA/czcTFDi mFaJg8RnrSK7dUPnMjBQduTH6Gl+Sy9cPdBD7+m/LGzWTMfgaUdXuiEdr/rNRP4L wsHMPQe09w/4shB9VzrKBXlkyJY0MLJuoDL3osMaxXLzcM7x1xkC/GHoFULOxPoy wtWRldbE0eHwVMH5l/IL8ybfTF9pm98c65m8bpbxQUfQmhNknanZtbr48pmoQODn 8byTMUpGbcpUjRLNkB7n6q0OCZXwiQ9bkSp/c3gVWvXYqz2iLPcJvZfh3hlrd/Bn K4whFw0= =h6jv -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210106' into staging qemu-sparc queue # gpg: Signature made Wed 06 Jan 2021 11:43:02 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20210106: sun4m: don't connect two qemu_irqs directly to the same input include/hw/sparc/grlib.h: Remove unused set_pil_in_fn typedef hw/sparc: Make grlib-irqmp device handle its own inbound IRQ lines hw/timer/slavio_timer: Allow 64-bit accesses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
30918661c1
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@ -51,6 +51,8 @@
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#define FORCE_OFFSET 0x80
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#define EXTENDED_OFFSET 0xC0
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#define MAX_PILS 16
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OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP)
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typedef struct IRQMPState IRQMPState;
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@ -126,7 +128,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno)
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grlib_irqmp_ack_mask(state, mask);
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}
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void grlib_irqmp_set_irq(void *opaque, int irq, int level)
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static void grlib_irqmp_set_irq(void *opaque, int irq, int level)
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{
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IRQMP *irqmp = GRLIB_IRQMP(opaque);
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IRQMPState *s;
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@ -328,6 +330,7 @@ static void grlib_irqmp_init(Object *obj)
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IRQMP *irqmp = GRLIB_IRQMP(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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qdev_init_gpio_in(DEVICE(obj), grlib_irqmp_set_irq, MAX_PILS);
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qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1);
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memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp,
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"irqmp", IRQMP_REG_SIZE);
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@ -14,6 +14,7 @@ config SUN4M
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select M48T59
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select STP2000
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select CHRP_NVRAM
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select OR_IRQ
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config LEON3
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bool
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@ -52,8 +52,6 @@
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#define LEON3_PROM_OFFSET (0x00000000)
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#define LEON3_RAM_OFFSET (0x40000000)
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#define MAX_PILS 16
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#define LEON3_UART_OFFSET (0x80000100)
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#define LEON3_UART_IRQ (3)
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@ -194,11 +192,10 @@ static void leon3_generic_hw_init(MachineState *machine)
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MemoryRegion *prom = g_new(MemoryRegion, 1);
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int ret;
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char *filename;
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qemu_irq *cpu_irqs = NULL;
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int bios_size;
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int prom_size;
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ResetData *reset_info;
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DeviceState *dev;
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DeviceState *dev, *irqmpdev;
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int i;
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AHBPnp *ahb_pnp;
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APBPnp *apb_pnp;
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@ -230,16 +227,15 @@ static void leon3_generic_hw_init(MachineState *machine)
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GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
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/* Allocate IRQ manager */
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dev = qdev_new(TYPE_GRLIB_IRQMP);
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irqmpdev = qdev_new(TYPE_GRLIB_IRQMP);
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qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
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env, "pil", 1);
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qdev_connect_gpio_out_named(dev, "grlib-irq", 0,
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qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0,
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qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
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env->irq_manager = dev;
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sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
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env->irq_manager = irqmpdev;
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env->qemu_irq_ack = leon3_irq_manager;
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cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq, dev, MAX_PILS);
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grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
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GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
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2, 0, GRLIB_APBIO_AREA);
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@ -330,7 +326,7 @@ static void leon3_generic_hw_init(MachineState *machine)
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
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for (i = 0; i < LEON3_TIMER_COUNT; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
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cpu_irqs[LEON3_TIMER_IRQ + i]);
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qdev_get_gpio_in(irqmpdev, LEON3_TIMER_IRQ + i));
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}
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grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
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@ -342,7 +338,8 @@ static void leon3_generic_hw_init(MachineState *machine)
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qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
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qdev_get_gpio_in(irqmpdev, LEON3_UART_IRQ));
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grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
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GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
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LEON3_UART_IRQ, GRLIB_APBIO_AREA);
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@ -50,6 +50,7 @@
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#include "hw/misc/empty_slot.h"
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#include "hw/misc/unimp.h"
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#include "hw/irq.h"
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#include "hw/or-irq.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "trace.h"
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@ -848,7 +849,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
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uint32_t initrd_size;
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DriveInfo *fd[MAX_FD];
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FWCfgState *fw_cfg;
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DeviceState *dev;
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DeviceState *dev, *ms_kb_orgate, *serial_orgate;
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SysBusDevice *s;
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unsigned int smp_cpus = machine->smp.cpus;
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unsigned int max_cpus = machine->smp.max_cpus;
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@ -994,10 +995,16 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
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qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_connect_irq(s, 0, slavio_irq[14]);
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sysbus_connect_irq(s, 1, slavio_irq[14]);
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sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
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/* Logically OR both its IRQs together */
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ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ));
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object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal);
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qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal);
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sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0));
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sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1));
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qdev_connect_gpio_out(DEVICE(ms_kb_orgate), 0, slavio_irq[14]);
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dev = qdev_new(TYPE_ESCC);
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qdev_prop_set_uint32(dev, "disabled", 0);
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qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
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@ -1009,10 +1016,17 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_connect_irq(s, 0, slavio_irq[15]);
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sysbus_connect_irq(s, 1, slavio_irq[15]);
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sysbus_mmio_map(s, 0, hwdef->serial_base);
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/* Logically OR both its IRQs together */
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serial_orgate = DEVICE(object_new(TYPE_OR_IRQ));
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object_property_set_int(OBJECT(serial_orgate), "num-lines", 2,
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&error_fatal);
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qdev_realize_and_unref(serial_orgate, NULL, &error_fatal);
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sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0));
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sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1));
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qdev_connect_gpio_out(DEVICE(serial_orgate), 0, slavio_irq[15]);
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if (hwdef->apc_base) {
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apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
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}
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@ -331,6 +331,10 @@ static const MemoryRegionOps slavio_timer_mem_ops = {
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.write = slavio_timer_mem_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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@ -34,10 +34,6 @@
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/* IRQMP */
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#define TYPE_GRLIB_IRQMP "grlib,irqmp"
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typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
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void grlib_irqmp_set_irq(void *opaque, int irq, int level);
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void grlib_irqmp_ack(DeviceState *dev, int intno);
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/* GPTimer */
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