hw/riscv: Always build riscv_hart.c
Every RISC-V machine needs riscv_hart hence there is no need to have a dedicated Kconfig option for it. Drop the Kconfig option and always build riscv_hart.c. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -1,6 +1,3 @@
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config HART
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bool
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config IBEX
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config IBEX
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bool
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bool
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@ -10,7 +7,6 @@ config SIFIVE
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config SIFIVE_E
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config SIFIVE_E
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bool
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bool
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select HART
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select SIFIVE
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select SIFIVE
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select SIFIVE_CLINT
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select SIFIVE_CLINT
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select SIFIVE_GPIO
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select SIFIVE_GPIO
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@ -22,7 +18,6 @@ config SIFIVE_E
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config SIFIVE_U
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config SIFIVE_U
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bool
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bool
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select CADENCE
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select CADENCE
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select HART
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select SIFIVE
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select SIFIVE
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select SIFIVE_CLINT
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select SIFIVE_CLINT
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select SIFIVE_GPIO
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select SIFIVE_GPIO
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@ -35,7 +30,6 @@ config SIFIVE_U
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config SPIKE
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config SPIKE
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bool
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bool
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select HART
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select HTIF
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select HTIF
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select SIFIVE
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select SIFIVE
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select SIFIVE_CLINT
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select SIFIVE_CLINT
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@ -44,7 +38,6 @@ config SPIKE
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config OPENTITAN
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config OPENTITAN
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bool
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bool
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select IBEX
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select IBEX
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select HART
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select UNIMP
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select UNIMP
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config RISCV_VIRT
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config RISCV_VIRT
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@ -52,7 +45,6 @@ config RISCV_VIRT
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imply PCI_DEVICES
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imply PCI_DEVICES
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imply TEST_DEVICES
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imply TEST_DEVICES
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select PCI
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select PCI
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select HART
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select SERIAL
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select SERIAL
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select GOLDFISH_RTC
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select GOLDFISH_RTC
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select VIRTIO_MMIO
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select VIRTIO_MMIO
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@ -65,7 +57,6 @@ config RISCV_VIRT
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config MICROCHIP_PFSOC
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config MICROCHIP_PFSOC
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bool
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bool
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select HART
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select SIFIVE
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select SIFIVE
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select SIFIVE_CLINT
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select SIFIVE_CLINT
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select UNIMP
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select UNIMP
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@ -1,7 +1,7 @@
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riscv_ss = ss.source_set()
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riscv_ss = ss.source_set()
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riscv_ss.add(files('boot.c'), fdt)
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riscv_ss.add(files('boot.c'), fdt)
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riscv_ss.add(files('numa.c'))
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riscv_ss.add(files('numa.c'))
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riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
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riscv_ss.add(files('riscv_hart.c'))
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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