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aspeed/scu: Fix W1C behavior

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This models the clock write one to clear registers, and fixes up some
incorrect behavior in all of the write to clear registers.

There was also a typo in one of the register definitions.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-8-clg@kaod.org
[clg: checkpatch.pl fixes ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Joel Stanley 2019-11-19 15:12:01 +01:00 committed by Peter Maydell
parent d3ff9e69b7
commit 310b5bc692
1 changed files with 14 additions and 5 deletions
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19
hw/misc/aspeed_scu.c
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@ -98,7 +98,7 @@
#define AST2600_CLK_STOP_CTRL TO_REG(0x80)
#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94)
#define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
#define AST2600_HPLL_PARAM TO_REG(0x200)
#define AST2600_HPLL_EXT TO_REG(0x204)
@ -532,11 +532,13 @@ static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
return s->regs[reg];
}
static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size)
static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
uint64_t data64, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@ -563,15 +565,22 @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data,
/* fall through */
case AST2600_SYS_RST_CTRL:
case AST2600_SYS_RST_CTRL2:
case AST2600_CLK_STOP_CTRL:
case AST2600_CLK_STOP_CTRL2:
/* W1S (Write 1 to set) registers */
s->regs[reg] |= data;
return;
case AST2600_SYS_RST_CTRL_CLR:
case AST2600_SYS_RST_CTRL2_CLR:
case AST2600_CLK_STOP_CTRL_CLR:
case AST2600_CLK_STOP_CTRL2_CLR:
case AST2600_HW_STRAP1_CLR:
case AST2600_HW_STRAP2_CLR:
/* W1C (Write 1 to clear) registers */
s->regs[reg] &= ~data;
/*
* W1C (Write 1 to clear) registers are offset by one address from
* the data register
*/
s->regs[reg - 1] &= ~data;
return;
case AST2600_RNG_DATA: