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target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T

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Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Filip Navara 2009-10-15 13:14:28 +02:00 committed by Aurelien Jarno
parent 396e467cb1
commit 3174f8e91f
1 changed files with 56 additions and 41 deletions
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97
target-arm/translate.c
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@ -6444,10 +6444,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
ARCH(6K); ARCH(6K);
else else
ARCH(6); ARCH(6);
gen_movl_T1_reg(s, rn); addr = tcg_temp_local_new_i32();
addr = cpu_T[1]; tcg_gen_mov_i32(addr, cpu_R[rn]);
if (insn & (1 << 20)) { if (insn & (1 << 20)) {
gen_helper_mark_exclusive(cpu_env, cpu_T[1]); gen_helper_mark_exclusive(cpu_env, addr);
switch (op1) { switch (op1) {
case 0: /* ldrex */ case 0: /* ldrex */
tmp = gen_ld32(addr, IS_USER(s)); tmp = gen_ld32(addr, IS_USER(s));
@ -6472,9 +6472,9 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
} else { } else {
int label = gen_new_label(); int label = gen_new_label();
rm = insn & 0xf; rm = insn & 0xf;
gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); tmp2 = tcg_temp_local_new_i32();
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], gen_helper_test_exclusive(tmp2, cpu_env, addr);
0, label); tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
tmp = load_reg(s,rm); tmp = load_reg(s,rm);
switch (op1) { switch (op1) {
case 0: /* strex */ case 0: /* strex */
@ -6496,8 +6496,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
abort(); abort();
} }
gen_set_label(label); gen_set_label(label);
gen_movl_reg_T0(s, rd); tcg_gen_mov_i32(cpu_R[rd], tmp2);
tcg_temp_free(tmp2);
} }
tcg_temp_free(addr);
} else { } else {
/* SWP instruction */ /* SWP instruction */
rm = (insn) & 0xf; rm = (insn) & 0xf;
@ -7238,22 +7240,24 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
} }
} else if ((insn & (1 << 23)) == 0) { } else if ((insn & (1 << 23)) == 0) {
/* Load/store exclusive word. */ /* Load/store exclusive word. */
gen_movl_T1_reg(s, rn); addr = tcg_temp_local_new();
addr = cpu_T[1]; tcg_gen_mov_i32(addr, cpu_R[rn]);
if (insn & (1 << 20)) { if (insn & (1 << 20)) {
gen_helper_mark_exclusive(cpu_env, cpu_T[1]); gen_helper_mark_exclusive(cpu_env, addr);
tmp = gen_ld32(addr, IS_USER(s)); tmp = gen_ld32(addr, IS_USER(s));
store_reg(s, rd, tmp); store_reg(s, rd, tmp);
} else { } else {
int label = gen_new_label(); int label = gen_new_label();
gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); tmp2 = tcg_temp_local_new();
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], gen_helper_test_exclusive(tmp2, cpu_env, addr);
0, label); tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
tmp = load_reg(s, rs); tmp = load_reg(s, rs);
gen_st32(tmp, cpu_T[1], IS_USER(s)); gen_st32(tmp, addr, IS_USER(s));
gen_set_label(label); gen_set_label(label);
gen_movl_reg_T0(s, rd); tcg_gen_mov_i32(cpu_R[rd], tmp2);
tcg_temp_free(tmp2);
} }
tcg_temp_free(addr);
} else if ((insn & (1 << 6)) == 0) { } else if ((insn & (1 << 6)) == 0) {
/* Table Branch. */ /* Table Branch. */
if (rn == 15) { if (rn == 15) {
@ -7283,10 +7287,8 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
we never have multiple CPUs running in parallel, we never have multiple CPUs running in parallel,
so it is good enough. */ so it is good enough. */
op = (insn >> 4) & 0x3; op = (insn >> 4) & 0x3;
/* Must use a global reg for the address because we have addr = tcg_temp_local_new();
a conditional branch in the store instruction. */ tcg_gen_mov_i32(addr, cpu_R[rn]);
gen_movl_T1_reg(s, rn);
addr = cpu_T[1];
if (insn & (1 << 20)) { if (insn & (1 << 20)) {
gen_helper_mark_exclusive(cpu_env, addr); gen_helper_mark_exclusive(cpu_env, addr);
switch (op) { switch (op) {
@ -7308,9 +7310,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
store_reg(s, rs, tmp); store_reg(s, rs, tmp);
} else { } else {
int label = gen_new_label(); int label = gen_new_label();
/* Must use a global that is not killed by the branch. */ tmp2 = tcg_temp_local_new();
gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); gen_helper_test_exclusive(tmp2, cpu_env, addr);
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], 0, label); tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
tmp = load_reg(s, rs); tmp = load_reg(s, rs);
switch (op) { switch (op) {
case 0: case 0:
@ -7329,8 +7331,10 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
goto illegal_op; goto illegal_op;
} }
gen_set_label(label); gen_set_label(label);
gen_movl_reg_T0(s, rm); tcg_gen_mov_i32(cpu_R[rm], tmp2);
tcg_temp_free(tmp2);
} }
tcg_temp_free(addr);
} }
} else { } else {
/* Load/store multiple, RFE, SRS. */ /* Load/store multiple, RFE, SRS. */
@ -7440,21 +7444,27 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
} }
break; break;
case 5: /* Data processing register constant shift. */ case 5: /* Data processing register constant shift. */
if (rn == 15) if (rn == 15) {
gen_op_movl_T0_im(0); tmp = new_tmp();
else tcg_gen_movi_i32(tmp, 0);
gen_movl_T0_reg(s, rn); } else {
gen_movl_T1_reg(s, rm); tmp = load_reg(s, rn);
}
tmp2 = load_reg(s, rm);
op = (insn >> 21) & 0xf; op = (insn >> 21) & 0xf;
shiftop = (insn >> 4) & 3; shiftop = (insn >> 4) & 3;
shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
conds = (insn & (1 << 20)) != 0; conds = (insn & (1 << 20)) != 0;
logic_cc = (conds && thumb2_logic_op(op)); logic_cc = (conds && thumb2_logic_op(op));
gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc); gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
if (gen_thumb2_data_op(s, op, conds, 0, cpu_T[0], cpu_T[1])) if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
goto illegal_op; goto illegal_op;
if (rd != 15) dead_tmp(tmp2);
gen_movl_reg_T0(s, rd); if (rd != 15) {
store_reg(s, rd, tmp);
} else {
dead_tmp(tmp);
}
break; break;
case 13: /* Misc data processing. */ case 13: /* Misc data processing. */
op = ((insn >> 22) & 6) | ((insn >> 7) & 1); op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
@ -7741,8 +7751,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
if (insn & (1 << 14)) { if (insn & (1 << 14)) {
/* Branch and link. */ /* Branch and link. */
gen_op_movl_T1_im(s->pc | 1); tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
gen_movl_reg_T1(s, 14);
} }
offset += s->pc; offset += s->pc;
@ -8005,19 +8014,25 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
shifter_out = 1; shifter_out = 1;
break; break;
} }
gen_op_movl_T1_im(imm); tmp2 = new_tmp();
tcg_gen_movi_i32(tmp2, imm);
rn = (insn >> 16) & 0xf; rn = (insn >> 16) & 0xf;
if (rn == 15) if (rn == 15) {
gen_op_movl_T0_im(0); tmp = new_tmp();
else tcg_gen_movi_i32(tmp, 0);
gen_movl_T0_reg(s, rn); } else {
tmp = load_reg(s, rn);
}
op = (insn >> 21) & 0xf; op = (insn >> 21) & 0xf;
if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
shifter_out, cpu_T[0], cpu_T[1])) shifter_out, tmp, tmp2))
goto illegal_op; goto illegal_op;
dead_tmp(tmp2);
rd = (insn >> 8) & 0xf; rd = (insn >> 8) & 0xf;
if (rd != 15) { if (rd != 15) {
gen_movl_reg_T0(s, rd); store_reg(s, rd, tmp);
} else {
dead_tmp(tmp);
} }
} }
} }