RISC-V Patches for the 5.0 Soft Freeze, Part 5
This tag contains the last of the patches I'd like to target for the 5.0 soft freeze. At this point we're mostly collecting fixes, but there are a few new features. The changes include: * An OpenSBI update, including the various bits necessary to put CI together and an image for the 32-bit sifive_u board. * A fix that disallows TSR when outside of machine mode. * A fix for VS-mode interrupt forwarding. -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAl5wSz4THHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYicR+D/9KZs8PxEKSG1fL6/ZYwHxtbDfwhBDu vtpBn1nxgXjbPmzCjGjFmldULKu9lJLSSZ7tLRKmMdaWDdKo2kTZ55h7NEkMxoxT xy9LYsiaM3adbkBArRhME9XRx1lh6LbVuvUhq4qx4Hn2xROQnWJ9tA1kNs0BApRx tIKmN71BtJM4NVZExdiX929UfyT6IZUbQlTpq1pEyucvUia+rvCnCg+ZTnSQbPiT NQc327vmcOTZWAT41KuitHLH79ijqd6tqnbkeOp57BRUoGnGM0S3zREUVuF9cpgh hQSDUOBu8xLzryR75oVXHOYJSTRqVwE9DaWQ45LRCgYYVgbSvqRuwICI038WEjtV Y1ZFBEl8/3wKEv30l+K4qDZ+TlNWBu4epdwSnEs1j0dOwaUvUIsEWnKslJr5tjKc E+CC9KZeci+J34MUqzwKeQolvpd9ng1c1DKPKdWnw//2Pl6aeH4XG9ZuuFE2/+K5 gWuCd25guUpmlp+oa+S+5F/9YvwZEubS6DJquabEK3J0eoDOZZPYaPX6LCG+e91P 2Q3jIh6k65GyN3wYv1H9yNY23hE99AaVUK6f8fMwyLc+iXSbPoQI0kHH3LHxOhOU dogRKsMS8nWF+x+wzTicLJl4tH2l8ra9R8AfhUMaQGugimvK/5fZreRk5532RiPy m8qEu9Ablinv2Q== =is1w -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf5' into staging RISC-V Patches for the 5.0 Soft Freeze, Part 5 This tag contains the last of the patches I'd like to target for the 5.0 soft freeze. At this point we're mostly collecting fixes, but there are a few new features. The changes include: * An OpenSBI update, including the various bits necessary to put CI together and an image for the 32-bit sifive_u board. * A fix that disallows TSR when outside of machine mode. * A fix for VS-mode interrupt forwarding. # gpg: Signature made Tue 17 Mar 2020 03:59:58 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * remotes/palmer/tags/riscv-for-master-5.0-sf5: target/riscv: Fix VS mode interrupts forwarding. gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries riscv: sifive_u: Update BIOS_FILENAME for 32-bit roms: opensbi: Add 32-bit firmware image for sifive_u machine roms: opensbi: Upgrade from v0.5 to v0.6 target/riscv: Correctly implement TSR trap Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
3189e9d38c
63
.gitlab-ci-opensbi.yml
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63
.gitlab-ci-opensbi.yml
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@ -0,0 +1,63 @@
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docker-opensbi:
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stage: build
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rules: # Only run this job when the Dockerfile is modified
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- changes:
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- .gitlab-ci-opensbi.yml
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- .gitlab-ci.d/opensbi/Dockerfile
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when: always
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image: docker:19.03.1
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services:
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- docker:19.03.1-dind
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variables:
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GIT_DEPTH: 3
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IMAGE_TAG: $CI_REGISTRY_IMAGE:opensbi-cross-build
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# We don't use TLS
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DOCKER_HOST: tcp://docker:2375
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DOCKER_TLS_CERTDIR: ""
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before_script:
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- docker login -u $CI_REGISTRY_USER -p $CI_REGISTRY_PASSWORD $CI_REGISTRY
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script:
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- docker pull $IMAGE_TAG || true
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- docker build --cache-from $IMAGE_TAG --tag $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA
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--tag $IMAGE_TAG .gitlab-ci.d/opensbi
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- docker push $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA
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- docker push $IMAGE_TAG
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build-opensbi:
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rules: # Only run this job when ...
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- changes: # ... roms/opensbi/ is modified (submodule updated)
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- roms/opensbi/*
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when: always
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- if: '$CI_COMMIT_REF_NAME =~ /^opensbi/' # or the branch/tag starts with 'opensbi'
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when: always
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- if: '$CI_COMMIT_MESSAGE =~ /opensbi/i' # or last commit description contains 'OpenSBI'
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when: always
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artifacts:
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paths: # 'artifacts.zip' will contains the following files:
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- pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
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- pc-bios/opensbi-riscv32-virt-fw_jump.bin
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- pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
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- pc-bios/opensbi-riscv64-virt-fw_jump.bin
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- opensbi32-virt-stdout.log
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- opensbi32-virt-stderr.log
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- opensbi64-virt-stdout.log
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- opensbi64-virt-stderr.log
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- opensbi32-sifive_u-stdout.log
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- opensbi32-sifive_u-stderr.log
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- opensbi64-sifive_u-stdout.log
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- opensbi64-sifive_u-stderr.log
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image: $CI_REGISTRY_IMAGE:opensbi-cross-build
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variables:
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GIT_DEPTH: 3
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script: # Clone the required submodules and build OpenSBI
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- git submodule update --init roms/opensbi
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- export JOBS=$(($(getconf _NPROCESSORS_ONLN) + 1))
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- echo "=== Using ${JOBS} simultaneous jobs ==="
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- make -j${JOBS} -C roms/opensbi clean
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- make -j${JOBS} -C roms opensbi32-virt 2>&1 1>opensbi32-virt-stdout.log | tee -a opensbi32-virt-stderr.log >&2
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- make -j${JOBS} -C roms/opensbi clean
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- make -j${JOBS} -C roms opensbi64-virt 2>&1 1>opensbi64-virt-stdout.log | tee -a opensbi64-virt-stderr.log >&2
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- make -j${JOBS} -C roms/opensbi clean
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- make -j${JOBS} -C roms opensbi32-sifive_u 2>&1 1>opensbi32-sifive_u-stdout.log | tee -a opensbi32-sifive_u-stderr.log >&2
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- make -j${JOBS} -C roms/opensbi clean
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- make -j${JOBS} -C roms opensbi64-sifive_u 2>&1 1>opensbi64-sifive_u-stdout.log | tee -a opensbi64-sifive_u-stderr.log >&2
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33
.gitlab-ci.d/opensbi/Dockerfile
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33
.gitlab-ci.d/opensbi/Dockerfile
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@ -0,0 +1,33 @@
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#
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# Docker image to cross-compile OpenSBI firmware binaries
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#
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FROM ubuntu:18.04
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MAINTAINER Bin Meng <bmeng.cn@gmail.com>
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# Install packages required to build OpenSBI
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RUN apt update \
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&& \
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\
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DEBIAN_FRONTEND=noninteractive \
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apt install --assume-yes --no-install-recommends \
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build-essential \
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ca-certificates \
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git \
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make \
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wget \
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&& \
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\
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rm -rf /var/lib/apt/lists/*
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# Manually install the kernel.org "Crosstool" based toolchains for gcc-8.3
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RUN wget -O - \
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https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8.3.0/x86_64-gcc-8.3.0-nolibc-riscv32-linux.tar.xz \
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| tar -C /opt -xJ
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RUN wget -O - \
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https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8.3.0/x86_64-gcc-8.3.0-nolibc-riscv64-linux.tar.xz \
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| tar -C /opt -xJ
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# Export the toolchains to the system path
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ENV PATH="/opt/gcc-8.3.0-nolibc/riscv32-linux/bin:${PATH}"
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ENV PATH="/opt/gcc-8.3.0-nolibc/riscv64-linux/bin:${PATH}"
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@ -1,5 +1,6 @@
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include:
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include:
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- local: '/.gitlab-ci-edk2.yml'
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- local: '/.gitlab-ci-edk2.yml'
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- local: '/.gitlab-ci-opensbi.yml'
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before_script:
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before_script:
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- apt-get update -qq
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- apt-get update -qq
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2
Makefile
2
Makefile
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@ -848,7 +848,7 @@ u-boot.e500 u-boot-sam460-20100605.bin \
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qemu_vga.ndrv \
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qemu_vga.ndrv \
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edk2-licenses.txt \
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edk2-licenses.txt \
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hppa-firmware.img \
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hppa-firmware.img \
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opensbi-riscv32-virt-fw_jump.bin \
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opensbi-riscv32-sifive_u-fw_jump.bin opensbi-riscv32-virt-fw_jump.bin \
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opensbi-riscv64-sifive_u-fw_jump.bin opensbi-riscv64-virt-fw_jump.bin
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opensbi-riscv64-sifive_u-fw_jump.bin opensbi-riscv64-virt-fw_jump.bin
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@ -56,7 +56,11 @@
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#include <libfdt.h>
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#include <libfdt.h>
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#define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
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#if defined(TARGET_RISCV32)
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# define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin"
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#else
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# define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
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#endif
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static const struct MemmapEntry {
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr base;
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BIN
pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
Normal file
BIN
pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
Normal file
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Binary file not shown.
Binary file not shown.
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@ -66,6 +66,7 @@ default help:
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@echo " efi -- update UEFI (edk2) platform firmware"
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@echo " efi -- update UEFI (edk2) platform firmware"
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@echo " opensbi32-virt -- update OpenSBI for 32-bit virt machine"
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@echo " opensbi32-virt -- update OpenSBI for 32-bit virt machine"
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@echo " opensbi64-virt -- update OpenSBI for 64-bit virt machine"
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@echo " opensbi64-virt -- update OpenSBI for 64-bit virt machine"
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@echo " opensbi32-sifive_u -- update OpenSBI for 32-bit sifive_u machine"
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@echo " opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u machine"
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@echo " opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u machine"
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@echo " bios-microvm -- update bios-microvm.bin (qboot)"
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@echo " bios-microvm -- update bios-microvm.bin (qboot)"
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@echo " clean -- delete the files generated by the previous" \
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@echo " clean -- delete the files generated by the previous" \
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@ -181,6 +182,12 @@ opensbi64-virt:
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PLATFORM="qemu/virt"
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PLATFORM="qemu/virt"
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cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-virt-fw_jump.bin
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cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-virt-fw_jump.bin
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opensbi32-sifive_u:
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$(MAKE) -C opensbi \
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CROSS_COMPILE=$(riscv32_cross_prefix) \
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PLATFORM="sifive/fu540"
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cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin ../pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
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opensbi64-sifive_u:
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opensbi64-sifive_u:
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$(MAKE) -C opensbi \
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$(MAKE) -C opensbi \
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CROSS_COMPILE=$(riscv64_cross_prefix) \
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CROSS_COMPILE=$(riscv64_cross_prefix) \
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@ -1 +1 @@
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Subproject commit be92da280d87c38a2e0adc5d3f43bab7b5468f09
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Subproject commit ac5e821d50be631f26274765a59bc1b444ffd862
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@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
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target_ulong pending = env->mip & env->mie &
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target_ulong pending = env->mip & env->mie &
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~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
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~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
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target_ulong vspending = (env->mip & env->mie &
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target_ulong vspending = (env->mip & env->mie &
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(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
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(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
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target_ulong mie = env->priv < PRV_M ||
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target_ulong mie = env->priv < PRV_M ||
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(env->priv == PRV_M && mstatus_mie);
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(env->priv == PRV_M && mstatus_mie);
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@ -907,6 +907,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
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if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
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!force_hs_execp) {
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!force_hs_execp) {
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/*
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* See if we need to adjust cause. Yes if its VS mode interrupt
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* no if hypervisor has delegated one of hs mode's interrupt
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*/
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if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
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cause == IRQ_VS_EXT)
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cause = cause - 1;
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/* Trap to VS mode */
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/* Trap to VS mode */
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} else if (riscv_cpu_virt_enabled(env)) {
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} else if (riscv_cpu_virt_enabled(env)) {
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/* Trap into HS mode, from virt */
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/* Trap into HS mode, from virt */
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@ -85,7 +85,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
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}
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}
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if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
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if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
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get_field(env->mstatus, MSTATUS_TSR)) {
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get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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}
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|
||||||
|
|
Loading…
Reference in a new issue