ppc/pnv: add a OCC model class
To ease the introduction of the OCC model for POWER9, provide a new class attributes to define XSCOM operations per CPU family and a PSI IRQ number. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190307223548.20516-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -790,7 +790,7 @@ static void pnv_chip_power8_instance_init(Object *obj)
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OBJECT(&chip8->psi), &error_abort);
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OBJECT(&chip8->psi), &error_abort);
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object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
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object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
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TYPE_PNV_OCC, &error_abort, NULL);
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TYPE_PNV8_OCC, &error_abort, NULL);
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object_property_add_const_link(OBJECT(&chip8->occ), "psi",
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object_property_add_const_link(OBJECT(&chip8->occ), "psi",
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OBJECT(&chip8->psi), &error_abort);
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OBJECT(&chip8->psi), &error_abort);
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}
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}
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@ -34,15 +34,17 @@
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static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
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static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
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{
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{
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bool irq_state;
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bool irq_state;
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PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
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val &= 0xffff000000000000ull;
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val &= 0xffff000000000000ull;
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occ->occmisc = val;
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occ->occmisc = val;
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irq_state = !!(val >> 63);
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irq_state = !!(val >> 63);
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pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state);
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pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
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}
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}
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static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned size)
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static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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{
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PnvOCC *occ = PNV_OCC(opaque);
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PnvOCC *occ = PNV_OCC(opaque);
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uint32_t offset = addr >> 3;
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uint32_t offset = addr >> 3;
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@ -54,13 +56,13 @@ static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned size)
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break;
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break;
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default:
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default:
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr);
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HWADDR_PRIx "\n", addr >> 3);
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}
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}
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return val;
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return val;
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}
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}
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static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
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static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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uint64_t val, unsigned size)
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{
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{
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PnvOCC *occ = PNV_OCC(opaque);
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PnvOCC *occ = PNV_OCC(opaque);
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uint32_t offset = addr >> 3;
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uint32_t offset = addr >> 3;
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@ -77,13 +79,13 @@ static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
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break;
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break;
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default:
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default:
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr);
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HWADDR_PRIx "\n", addr >> 3);
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}
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}
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}
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}
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static const MemoryRegionOps pnv_occ_xscom_ops = {
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static const MemoryRegionOps pnv_occ_power8_xscom_ops = {
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.read = pnv_occ_xscom_read,
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.read = pnv_occ_power8_xscom_read,
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.write = pnv_occ_xscom_write,
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.write = pnv_occ_power8_xscom_write,
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.valid.min_access_size = 8,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.min_access_size = 8,
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@ -91,27 +93,42 @@ static const MemoryRegionOps pnv_occ_xscom_ops = {
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.endianness = DEVICE_BIG_ENDIAN,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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};
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static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
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{
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PnvOCCClass *poc = PNV_OCC_CLASS(klass);
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poc->xscom_size = PNV_XSCOM_OCC_SIZE;
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poc->xscom_ops = &pnv_occ_power8_xscom_ops;
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poc->psi_irq = PSIHB_IRQ_OCC;
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}
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static const TypeInfo pnv_occ_power8_type_info = {
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.name = TYPE_PNV8_OCC,
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.parent = TYPE_PNV_OCC,
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.instance_size = sizeof(PnvOCC),
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.class_init = pnv_occ_power8_class_init,
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};
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static void pnv_occ_realize(DeviceState *dev, Error **errp)
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static void pnv_occ_realize(DeviceState *dev, Error **errp)
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{
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{
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PnvOCC *occ = PNV_OCC(dev);
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PnvOCC *occ = PNV_OCC(dev);
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PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
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Object *obj;
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Object *obj;
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Error *error = NULL;
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Error *local_err = NULL;
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occ->occmisc = 0;
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occ->occmisc = 0;
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/* get PSI object from chip */
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obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
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obj = object_property_get_link(OBJECT(dev), "psi", &error);
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if (!obj) {
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if (!obj) {
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error_setg(errp, "%s: required link 'psi' not found: %s",
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error_propagate(errp, local_err);
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__func__, error_get_pretty(error));
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error_prepend(errp, "required link 'psi' not found: ");
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return;
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return;
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}
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}
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occ->psi = PNV_PSI(obj);
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occ->psi = PNV_PSI(obj);
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/* XScom region for OCC registers */
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/* XScom region for OCC registers */
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pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_ops,
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pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
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occ, "xscom-occ", PNV_XSCOM_OCC_SIZE);
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occ, "xscom-occ", poc->xscom_size);
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}
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}
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static void pnv_occ_class_init(ObjectClass *klass, void *data)
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static void pnv_occ_class_init(ObjectClass *klass, void *data)
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@ -119,6 +136,7 @@ static void pnv_occ_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = pnv_occ_realize;
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dc->realize = pnv_occ_realize;
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dc->desc = "PowerNV OCC Controller";
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}
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}
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static const TypeInfo pnv_occ_type_info = {
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static const TypeInfo pnv_occ_type_info = {
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@ -126,11 +144,14 @@ static const TypeInfo pnv_occ_type_info = {
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.parent = TYPE_DEVICE,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvOCC),
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.instance_size = sizeof(PnvOCC),
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.class_init = pnv_occ_class_init,
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.class_init = pnv_occ_class_init,
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.class_size = sizeof(PnvOCCClass),
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.abstract = true,
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};
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};
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static void pnv_occ_register_types(void)
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static void pnv_occ_register_types(void)
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{
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{
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type_register_static(&pnv_occ_type_info);
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type_register_static(&pnv_occ_type_info);
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type_register_static(&pnv_occ_power8_type_info);
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}
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}
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type_init(pnv_occ_register_types)
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type_init(pnv_occ_register_types);
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@ -23,6 +23,8 @@
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#define TYPE_PNV_OCC "pnv-occ"
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#define TYPE_PNV_OCC "pnv-occ"
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#define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC)
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#define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC)
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#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8"
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#define PNV8_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV8_OCC)
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typedef struct PnvOCC {
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typedef struct PnvOCC {
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DeviceState xd;
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DeviceState xd;
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@ -35,4 +37,17 @@ typedef struct PnvOCC {
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MemoryRegion xscom_regs;
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MemoryRegion xscom_regs;
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} PnvOCC;
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} PnvOCC;
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#define PNV_OCC_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvOCCClass, (klass), TYPE_PNV_OCC)
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#define PNV_OCC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvOCCClass, (obj), TYPE_PNV_OCC)
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typedef struct PnvOCCClass {
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DeviceClass parent_class;
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int xscom_size;
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const MemoryRegionOps *xscom_ops;
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int psi_irq;
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} PnvOCCClass;
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#endif /* _PPC_PNV_OCC_H */
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#endif /* _PPC_PNV_OCC_H */
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