hw/timer/armv7m_systick: Rewrite to use ptimers
The armv7m systick timer is a 24-bit decrementing, wrap-on-zero, clear-on-write counter. Our current implementation has various bugs and dubious workarounds in it (for instance see https://bugs.launchpad.net/qemu/+bug/1872237). We have an implementation of a simple decrementing counter and we put a lot of effort into making sure it handles the interesting corner cases (like "spend a cycle at 0 before reloading") -- ptimer. Rewrite the systick timer to use a ptimer rather than a raw QEMU timer. Unfortunately this is a migration compatibility break, which will affect all M-profile boards. Among other bugs, this fixes https://bugs.launchpad.net/qemu/+bug/1872237 : now writes to SYST_CVR when the timer is enabled correctly do nothing; when the timer is enabled via SYST_CSR.ENABLE, the ptimer code will (because of POLICY_NO_IMMEDIATE_RELOAD) arrange that after one timer tick the counter is reloaded from SYST_RVR and then counts down from there, as the architecture requires. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201015151829.14656-3-peter.maydell@linaro.org
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@ -39,26 +39,6 @@ static inline int64_t systick_scale(SysTickState *s)
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}
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}
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}
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}
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static void systick_reload(SysTickState *s, int reset)
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{
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/* The Cortex-M3 Devices Generic User Guide says that "When the
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* ENABLE bit is set to 1, the counter loads the RELOAD value from the
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* SYST RVR register and then counts down". So, we need to check the
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* ENABLE bit before reloading the value.
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*/
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trace_systick_reload();
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if ((s->control & SYSTICK_ENABLE) == 0) {
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return;
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}
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if (reset) {
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s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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}
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s->tick += (s->reload + 1) * systick_scale(s);
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timer_mod(s->timer, s->tick);
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}
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static void systick_timer_tick(void *opaque)
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static void systick_timer_tick(void *opaque)
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{
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{
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SysTickState *s = (SysTickState *)opaque;
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SysTickState *s = (SysTickState *)opaque;
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@ -70,10 +50,12 @@ static void systick_timer_tick(void *opaque)
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/* Tell the NVIC to pend the SysTick exception */
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/* Tell the NVIC to pend the SysTick exception */
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qemu_irq_pulse(s->irq);
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qemu_irq_pulse(s->irq);
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}
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}
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if (s->reload == 0) {
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if (ptimer_get_limit(s->ptimer) == 0) {
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s->control &= ~SYSTICK_ENABLE;
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/*
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} else {
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* Timer expiry with SYST_RVR zero disables the timer
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systick_reload(s, 0);
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* (but doesn't clear SYST_CSR.ENABLE)
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*/
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ptimer_stop(s->ptimer);
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}
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}
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}
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}
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@ -94,30 +76,11 @@ static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,
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s->control &= ~SYSTICK_COUNTFLAG;
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s->control &= ~SYSTICK_COUNTFLAG;
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break;
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break;
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case 0x4: /* SysTick Reload Value. */
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case 0x4: /* SysTick Reload Value. */
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val = s->reload;
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val = ptimer_get_limit(s->ptimer);
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break;
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break;
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case 0x8: /* SysTick Current Value. */
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case 0x8: /* SysTick Current Value. */
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{
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val = ptimer_get_count(s->ptimer);
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int64_t t;
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if ((s->control & SYSTICK_ENABLE) == 0) {
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val = 0;
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break;
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break;
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}
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t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if (t >= s->tick) {
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val = 0;
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break;
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}
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val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
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/* The interrupt in triggered when the timer reaches zero.
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However the counter is not reloaded until the next clock
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tick. This is a hack to return zero during the first tick. */
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if (val > s->reload) {
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val = 0;
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}
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break;
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}
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case 0xc: /* SysTick Calibration Value. */
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case 0xc: /* SysTick Calibration Value. */
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val = 10000;
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val = 10000;
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break;
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break;
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@ -149,39 +112,50 @@ static MemTxResult systick_write(void *opaque, hwaddr addr,
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switch (addr) {
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switch (addr) {
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case 0x0: /* SysTick Control and Status. */
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case 0x0: /* SysTick Control and Status. */
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{
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{
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uint32_t oldval = s->control;
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uint32_t oldval;
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ptimer_transaction_begin(s->ptimer);
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oldval = s->control;
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s->control &= 0xfffffff8;
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s->control &= 0xfffffff8;
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s->control |= value & 7;
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s->control |= value & 7;
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if ((oldval ^ value) & SYSTICK_ENABLE) {
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if ((oldval ^ value) & SYSTICK_ENABLE) {
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if (value & SYSTICK_ENABLE) {
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if (value & SYSTICK_ENABLE) {
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if (s->tick) {
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/*
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s->tick += now;
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* Always reload the period in case board code has
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timer_mod(s->timer, s->tick);
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* changed system_clock_scale. If we ever replace that
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* global with a more sensible API then we might be able
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* to set the period only when it actually changes.
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*/
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ptimer_set_period(s->ptimer, systick_scale(s));
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ptimer_run(s->ptimer, 0);
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} else {
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} else {
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systick_reload(s, 1);
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ptimer_stop(s->ptimer);
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}
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} else {
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timer_del(s->timer);
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s->tick -= now;
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if (s->tick < 0) {
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s->tick = 0;
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}
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}
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}
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} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
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} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
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/* This is a hack. Force the timer to be reloaded
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ptimer_set_period(s->ptimer, systick_scale(s));
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when the reference clock is changed. */
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systick_reload(s, 1);
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}
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}
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ptimer_transaction_commit(s->ptimer);
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break;
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break;
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}
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}
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case 0x4: /* SysTick Reload Value. */
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case 0x4: /* SysTick Reload Value. */
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s->reload = value;
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ptimer_transaction_begin(s->ptimer);
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ptimer_set_limit(s->ptimer, value & 0xffffff, 0);
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ptimer_transaction_commit(s->ptimer);
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break;
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break;
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case 0x8: /* SysTick Current Value. Writes reload the timer. */
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case 0x8: /* SysTick Current Value. */
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systick_reload(s, 1);
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/*
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* Writing any value clears SYST_CVR to zero and clears
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* SYST_CSR.COUNTFLAG. The counter will then reload from SYST_RVR
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* on the next clock edge unless SYST_RVR is zero.
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*/
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ptimer_transaction_begin(s->ptimer);
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if (ptimer_get_limit(s->ptimer) == 0) {
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ptimer_stop(s->ptimer);
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}
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ptimer_set_count(s->ptimer, 0);
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s->control &= ~SYSTICK_COUNTFLAG;
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s->control &= ~SYSTICK_COUNTFLAG;
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ptimer_transaction_commit(s->ptimer);
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break;
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break;
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default:
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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qemu_log_mask(LOG_GUEST_ERROR,
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@ -210,10 +184,13 @@ static void systick_reset(DeviceState *dev)
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*/
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*/
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assert(system_clock_scale != 0);
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assert(system_clock_scale != 0);
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ptimer_transaction_begin(s->ptimer);
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s->control = 0;
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s->control = 0;
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s->reload = 0;
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ptimer_stop(s->ptimer);
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s->tick = 0;
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ptimer_set_count(s->ptimer, 0);
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timer_del(s->timer);
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ptimer_set_limit(s->ptimer, 0, 0);
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ptimer_set_period(s->ptimer, systick_scale(s));
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ptimer_transaction_commit(s->ptimer);
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}
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}
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static void systick_instance_init(Object *obj)
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static void systick_instance_init(Object *obj)
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@ -229,18 +206,21 @@ static void systick_instance_init(Object *obj)
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static void systick_realize(DeviceState *dev, Error **errp)
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static void systick_realize(DeviceState *dev, Error **errp)
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{
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{
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SysTickState *s = SYSTICK(dev);
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SysTickState *s = SYSTICK(dev);
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
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s->ptimer = ptimer_init(systick_timer_tick, s,
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PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
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PTIMER_POLICY_NO_COUNTER_ROUND_DOWN |
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PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
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PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
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}
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}
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static const VMStateDescription vmstate_systick = {
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static const VMStateDescription vmstate_systick = {
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.name = "armv7m_systick",
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.name = "armv7m_systick",
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.version_id = 1,
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(control, SysTickState),
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VMSTATE_UINT32(control, SysTickState),
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VMSTATE_UINT32(reload, SysTickState),
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VMSTATE_INT64(tick, SysTickState),
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VMSTATE_INT64(tick, SysTickState),
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VMSTATE_TIMER_PTR(timer, SysTickState),
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VMSTATE_PTIMER(ptimer, SysTickState),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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}
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}
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};
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};
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@ -14,6 +14,7 @@
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#include "qom/object.h"
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#include "hw/ptimer.h"
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#define TYPE_SYSTICK "armv7m_systick"
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#define TYPE_SYSTICK "armv7m_systick"
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@ -27,7 +28,7 @@ struct SysTickState {
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uint32_t control;
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uint32_t control;
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uint32_t reload;
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uint32_t reload;
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int64_t tick;
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int64_t tick;
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QEMUTimer *timer;
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ptimer_state *ptimer;
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MemoryRegion iomem;
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq irq;
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};
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};
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