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target/ppc: Move SPR_DSISR setting to powerpc_excp

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By doing this while sending the exception, we will have already
done the unwinding, which makes the ppc_cpu_do_unaligned_access
code a bit cleaner.

Update the comment about the expected instruction format.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-07-29 13:17:35 -10:00
parent b414df757d
commit 336e91f853
1 changed files with 9 additions and 12 deletions
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21
target/ppc/excp_helper.c
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@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*
* Note: the opcode fields will not be set properly for a
* direct store load/store, but nobody cares as nobody
* actually uses direct store segments.
* Get rS/rD and rA from faulting opcode.
* Note: We will only invoke ALIGN for atomic operations,
* so all instructions are X-form.
*/
env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
{
uint32_t insn = cpu_ldl_code(env, env->nip);
env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16;
}
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
int mmu_idx, uintptr_t retaddr)
{
CPUPPCState *env = cs->env_ptr;
uint32_t insn;
/* Restore state and reload the insn we executed, for filling in DSISR. */
cpu_restore_state(cs, retaddr, true);
insn = cpu_ldl_code(env, env->nip);
cs->exception_index = POWERPC_EXCP_ALIGN;
env->error_code = insn & 0x03FF0000;
cpu_loop_exit(cs);
env->error_code = 0;
cpu_loop_exit_restore(cs, retaddr);
}
#endif