target/ppc: Move SPR_DSISR setting to powerpc_excp
By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
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break;
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break;
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}
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}
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case POWERPC_EXCP_ALIGN: /* Alignment exception */
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case POWERPC_EXCP_ALIGN: /* Alignment exception */
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/* Get rS/rD and rA from faulting opcode */
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/*
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/*
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* Note: the opcode fields will not be set properly for a
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* Get rS/rD and rA from faulting opcode.
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* direct store load/store, but nobody cares as nobody
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* Note: We will only invoke ALIGN for atomic operations,
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* actually uses direct store segments.
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* so all instructions are X-form.
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*/
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*/
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env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
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{
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uint32_t insn = cpu_ldl_code(env, env->nip);
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env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16;
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}
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break;
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break;
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case POWERPC_EXCP_PROGRAM: /* Program exception */
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case POWERPC_EXCP_PROGRAM: /* Program exception */
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switch (env->error_code & ~0xF) {
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switch (env->error_code & ~0xF) {
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@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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int mmu_idx, uintptr_t retaddr)
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int mmu_idx, uintptr_t retaddr)
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{
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{
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CPUPPCState *env = cs->env_ptr;
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CPUPPCState *env = cs->env_ptr;
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uint32_t insn;
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/* Restore state and reload the insn we executed, for filling in DSISR. */
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cpu_restore_state(cs, retaddr, true);
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insn = cpu_ldl_code(env, env->nip);
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cs->exception_index = POWERPC_EXCP_ALIGN;
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cs->exception_index = POWERPC_EXCP_ALIGN;
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env->error_code = insn & 0x03FF0000;
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env->error_code = 0;
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cpu_loop_exit(cs);
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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#endif
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#endif
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