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target/riscv: Remove shift and slt insn manual decoding

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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2019-02-13 07:54:05 -08:00
parent f2ab172867
commit 34446e8458
2 changed files with 82 additions and 72 deletions
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95
target/riscv/insn_trans/trans_rvi.inc.c
View file

@ -220,30 +220,25 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a)
return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
}
static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
}
static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
}
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
TCGv source1;
source1 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
return true;
return gen_arith_imm(ctx, a, &gen_slt);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
TCGv source1;
source1 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
return true;
return gen_arith_imm(ctx, a, &gen_sltu);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@ -322,20 +317,17 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
return true;
return gen_shift(ctx, a, &tcg_gen_shl_tl);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@ -345,14 +337,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
return true;
return gen_shift(ctx, a, &tcg_gen_shr_tl);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
return true;
return gen_shift(ctx, a, &tcg_gen_sar_tl);
}
static bool trans_or(DisasContext *ctx, arg_or *a)
@ -419,19 +409,62 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
tcg_gen_andi_tl(source2, source2, 0x1F);
tcg_gen_shl_tl(source1, source1, source2);
tcg_gen_ext32s_tl(source1, source1);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
/* clear upper 32 */
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_andi_tl(source2, source2, 0x1F);
tcg_gen_shr_tl(source1, source1, source2);
tcg_gen_ext32s_tl(source1, source1);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
/*
* first, trick to get it to act like working on 32 bits (get rid of
* upper 32, sign extend to fill space)
*/
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_andi_tl(source2, source2, 0x1F);
tcg_gen_sar_tl(source1, source1, source2);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
#endif

59
target/riscv/translate.c
View file

@ -198,47 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(source2, source2, 0x1F);
tcg_gen_shl_tl(source1, source1, source2);
break;
#endif
case OPC_RISC_SLL:
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_shl_tl(source1, source1, source2);
break;
case OPC_RISC_SLT:
tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2);
break;
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_andi_tl(source2, source2, 0x1F);
tcg_gen_shr_tl(source1, source1, source2);
break;
#endif
case OPC_RISC_SRL:
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_shr_tl(source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRAW:
/* first, trick to get it to act like working on 32 bits (get rid of
upper 32, sign extend to fill space) */
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_andi_tl(source2, source2, 0x1F);
tcg_gen_sar_tl(source1, source1, source2);
break;
#endif
case OPC_RISC_SRA:
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(source1, source1, source2);
break;
CASE_OP_32_64(OPC_RISC_MUL):
if (!has_ext(ctx, RVM)) {
goto do_illegal;
@ -742,6 +701,24 @@ static bool trans_arith(DisasContext *ctx, arg_r *a,
return true;
}
static bool gen_shift(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
(*func)(source1, source1, source2);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"