target-ppc: Bug Fix: srawi
For 64 bit implementations, the special case of a shift by zero should result in the sign extension of the least significant 32 bits of the source GPR (not a direct copy of the 64 bit source GPR). Example: R3 A6212433228F41DC srawi 3,3,0 R3 expected : 00000000228F41DC R3 actual : A6212433228F41DC (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -1944,7 +1944,7 @@ static void gen_srawi(DisasContext *ctx)
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TCGv dst = cpu_gpr[rA(ctx->opcode)];
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TCGv dst = cpu_gpr[rA(ctx->opcode)];
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TCGv src = cpu_gpr[rS(ctx->opcode)];
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TCGv src = cpu_gpr[rS(ctx->opcode)];
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if (sh == 0) {
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if (sh == 0) {
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tcg_gen_mov_tl(dst, src);
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tcg_gen_ext32s_tl(dst, src);
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tcg_gen_movi_tl(cpu_ca, 0);
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tcg_gen_movi_tl(cpu_ca, 0);
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} else {
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} else {
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TCGv t0;
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TCGv t0;
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