ppc: Convert PPC UIC to a QOM device
Currently the PPC UIC ("Universal Interrupt Controller") is implemented as a non-QOM device in ppc4xx_devs.c. Convert it to a proper QOM device in hw/intc. The ppcuic_init() function is retained for the moment with its current interface; in subsequent commits this will be tidied up to avoid the allocation of an irq array. This conversion adds VMState support. It leaves the LOG_UIC() macro as-is to maximise the extent to which this is simply code-movement rather than a rewrite (in new code it would be better to use tracepoints). The default property values for dcr-base and use-vectors are set to match those use by most of our boards with a UIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20201212001537.24520-3-peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
parent
59a958bb74
commit
34d0831f38
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@ -1680,6 +1680,8 @@ F: hw/ppc/ppc4*.c
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F: hw/i2c/ppc4xx_i2c.c
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F: hw/i2c/ppc4xx_i2c.c
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F: include/hw/ppc/ppc4xx.h
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F: include/hw/ppc/ppc4xx.h
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F: include/hw/i2c/ppc4xx_i2c.h
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F: include/hw/i2c/ppc4xx_i2c.h
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F: hw/intc/ppc-uic.c
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F: include/hw/intc/ppc-uic.h
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Character devices
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Character devices
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M: Marc-André Lureau <marcandre.lureau@redhat.com>
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M: Marc-André Lureau <marcandre.lureau@redhat.com>
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@ -62,6 +62,9 @@ config S390_FLIC_KVM
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config OMPIC
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config OMPIC
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bool
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bool
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config PPC_UIC
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bool
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config RX_ICU
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config RX_ICU
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bool
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bool
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@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c'))
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specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c'))
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specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c'))
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specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c'))
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specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c'))
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specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c'))
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specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c'))
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specific_ss.add(when: 'CONFIG_PPC_UIC', if_true: files('ppc-uic.c'))
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specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2836_control.c'))
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specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2836_control.c'))
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specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
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specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
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specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
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specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
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321
hw/intc/ppc-uic.c
Normal file
321
hw/intc/ppc-uic.c
Normal file
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@ -0,0 +1,321 @@
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/*
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* "Universal" Interrupt Controller for PowerPPC 4xx embedded processors
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "include/hw/intc/ppc-uic.h"
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#include "hw/irq.h"
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#include "cpu.h"
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#include "hw/ppc/ppc.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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enum {
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DCR_UICSR = 0x000,
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DCR_UICSRS = 0x001,
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DCR_UICER = 0x002,
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DCR_UICCR = 0x003,
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DCR_UICPR = 0x004,
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DCR_UICTR = 0x005,
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DCR_UICMSR = 0x006,
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DCR_UICVR = 0x007,
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DCR_UICVCR = 0x008,
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DCR_UICMAX = 0x009,
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};
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/*#define DEBUG_UIC*/
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#ifdef DEBUG_UIC
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# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
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#else
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# define LOG_UIC(...) do { } while (0)
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#endif
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static void ppcuic_trigger_irq(PPCUIC *uic)
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{
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uint32_t ir, cr;
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int start, end, inc, i;
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/* Trigger interrupt if any is pending */
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ir = uic->uicsr & uic->uicer & (~uic->uiccr);
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cr = uic->uicsr & uic->uicer & uic->uiccr;
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LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
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" uiccr %08" PRIx32 "\n"
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" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
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__func__, uic->uicsr, uic->uicer, uic->uiccr,
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uic->uicsr & uic->uicer, ir, cr);
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if (ir != 0x0000000) {
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LOG_UIC("Raise UIC interrupt\n");
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qemu_irq_raise(uic->output_int);
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} else {
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LOG_UIC("Lower UIC interrupt\n");
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qemu_irq_lower(uic->output_int);
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}
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/* Trigger critical interrupt if any is pending and update vector */
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if (cr != 0x0000000) {
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qemu_irq_raise(uic->output_cint);
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if (uic->use_vectors) {
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/* Compute critical IRQ vector */
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if (uic->uicvcr & 1) {
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start = 31;
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end = 0;
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inc = -1;
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} else {
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start = 0;
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end = 31;
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inc = 1;
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}
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uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
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for (i = start; i <= end; i += inc) {
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if (cr & (1 << i)) {
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uic->uicvr += (i - start) * 512 * inc;
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break;
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}
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}
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}
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LOG_UIC("Raise UIC critical interrupt - "
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"vector %08" PRIx32 "\n", uic->uicvr);
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} else {
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LOG_UIC("Lower UIC critical interrupt\n");
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qemu_irq_lower(uic->output_cint);
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uic->uicvr = 0x00000000;
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}
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}
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static void ppcuic_set_irq(void *opaque, int irq_num, int level)
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{
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PPCUIC *uic;
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uint32_t mask, sr;
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uic = opaque;
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mask = 1U << (31 - irq_num);
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LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
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" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
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__func__, irq_num, level,
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uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
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if (irq_num < 0 || irq_num > 31) {
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return;
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}
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sr = uic->uicsr;
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/* Update status register */
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if (uic->uictr & mask) {
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/* Edge sensitive interrupt */
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if (level == 1) {
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uic->uicsr |= mask;
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}
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} else {
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/* Level sensitive interrupt */
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if (level == 1) {
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uic->uicsr |= mask;
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uic->level |= mask;
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} else {
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uic->uicsr &= ~mask;
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uic->level &= ~mask;
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}
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}
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LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
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"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
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if (sr != uic->uicsr) {
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ppcuic_trigger_irq(uic);
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}
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}
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static uint32_t dcr_read_uic(void *opaque, int dcrn)
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{
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PPCUIC *uic;
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uint32_t ret;
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uic = opaque;
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dcrn -= uic->dcr_base;
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switch (dcrn) {
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case DCR_UICSR:
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case DCR_UICSRS:
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ret = uic->uicsr;
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break;
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case DCR_UICER:
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ret = uic->uicer;
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break;
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case DCR_UICCR:
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ret = uic->uiccr;
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break;
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case DCR_UICPR:
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ret = uic->uicpr;
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break;
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case DCR_UICTR:
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ret = uic->uictr;
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break;
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case DCR_UICMSR:
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ret = uic->uicsr & uic->uicer;
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break;
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case DCR_UICVR:
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if (!uic->use_vectors) {
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goto no_read;
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}
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ret = uic->uicvr;
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break;
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case DCR_UICVCR:
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if (!uic->use_vectors) {
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goto no_read;
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}
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ret = uic->uicvcr;
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break;
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default:
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no_read:
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ret = 0x00000000;
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break;
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}
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return ret;
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}
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static void dcr_write_uic(void *opaque, int dcrn, uint32_t val)
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{
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PPCUIC *uic;
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uic = opaque;
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dcrn -= uic->dcr_base;
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LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
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switch (dcrn) {
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case DCR_UICSR:
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uic->uicsr &= ~val;
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uic->uicsr |= uic->level;
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ppcuic_trigger_irq(uic);
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break;
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case DCR_UICSRS:
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uic->uicsr |= val;
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ppcuic_trigger_irq(uic);
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break;
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case DCR_UICER:
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uic->uicer = val;
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ppcuic_trigger_irq(uic);
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break;
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case DCR_UICCR:
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uic->uiccr = val;
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ppcuic_trigger_irq(uic);
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break;
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case DCR_UICPR:
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uic->uicpr = val;
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break;
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case DCR_UICTR:
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uic->uictr = val;
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ppcuic_trigger_irq(uic);
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break;
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case DCR_UICMSR:
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break;
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case DCR_UICVR:
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break;
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case DCR_UICVCR:
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uic->uicvcr = val & 0xFFFFFFFD;
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ppcuic_trigger_irq(uic);
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break;
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}
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}
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static void ppc_uic_reset(DeviceState *dev)
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{
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PPCUIC *uic = PPC_UIC(dev);
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uic->uiccr = 0x00000000;
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uic->uicer = 0x00000000;
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uic->uicpr = 0x00000000;
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uic->uicsr = 0x00000000;
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uic->uictr = 0x00000000;
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if (uic->use_vectors) {
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uic->uicvcr = 0x00000000;
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uic->uicvr = 0x0000000;
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}
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}
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static void ppc_uic_realize(DeviceState *dev, Error **errp)
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{
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PPCUIC *uic = PPC_UIC(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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PowerPCCPU *cpu;
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int i;
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if (!uic->cpu) {
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/* This is a programming error in the code using this device */
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error_setg(errp, "ppc-uic 'cpu' link property was not set");
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return;
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}
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cpu = POWERPC_CPU(uic->cpu);
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for (i = 0; i < DCR_UICMAX; i++) {
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ppc_dcr_register(&cpu->env, uic->dcr_base + i, uic,
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&dcr_read_uic, &dcr_write_uic);
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}
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sysbus_init_irq(sbd, &uic->output_int);
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sysbus_init_irq(sbd, &uic->output_cint);
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qdev_init_gpio_in(dev, ppcuic_set_irq, UIC_MAX_IRQ);
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}
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static Property ppc_uic_properties[] = {
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DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *),
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DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0x30),
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DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true),
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DEFINE_PROP_END_OF_LIST()
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};
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static const VMStateDescription ppc_uic_vmstate = {
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.name = "ppc-uic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(level, PPCUIC),
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VMSTATE_UINT32(uicsr, PPCUIC),
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VMSTATE_UINT32(uicer, PPCUIC),
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VMSTATE_UINT32(uiccr, PPCUIC),
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VMSTATE_UINT32(uicpr, PPCUIC),
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VMSTATE_UINT32(uictr, PPCUIC),
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VMSTATE_UINT32(uicvcr, PPCUIC),
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VMSTATE_UINT32(uicvr, PPCUIC),
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VMSTATE_END_OF_LIST()
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},
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};
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static void ppc_uic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = ppc_uic_reset;
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dc->realize = ppc_uic_realize;
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dc->vmsd = &ppc_uic_vmstate;
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device_class_set_props(dc, ppc_uic_properties);
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}
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static const TypeInfo ppc_uic_info = {
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.name = TYPE_PPC_UIC,
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|
.parent = TYPE_SYS_BUS_DEVICE,
|
||||||
|
.instance_size = sizeof(PPCUIC),
|
||||||
|
.class_init = ppc_uic_class_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void ppc_uic_register_types(void)
|
||||||
|
{
|
||||||
|
type_register_static(&ppc_uic_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(ppc_uic_register_types);
|
|
@ -53,6 +53,7 @@ config PPC4XX
|
||||||
bool
|
bool
|
||||||
select BITBANG_I2C
|
select BITBANG_I2C
|
||||||
select PCI
|
select PCI
|
||||||
|
select PPC_UIC
|
||||||
|
|
||||||
config SAM460EX
|
config SAM460EX
|
||||||
bool
|
bool
|
||||||
|
|
|
@ -30,9 +30,12 @@
|
||||||
#include "hw/ppc/ppc.h"
|
#include "hw/ppc/ppc.h"
|
||||||
#include "hw/ppc/ppc4xx.h"
|
#include "hw/ppc/ppc4xx.h"
|
||||||
#include "hw/boards.h"
|
#include "hw/boards.h"
|
||||||
|
#include "hw/intc/ppc-uic.h"
|
||||||
|
#include "hw/qdev-properties.h"
|
||||||
#include "qemu/log.h"
|
#include "qemu/log.h"
|
||||||
#include "exec/address-spaces.h"
|
#include "exec/address-spaces.h"
|
||||||
#include "qemu/error-report.h"
|
#include "qemu/error-report.h"
|
||||||
|
#include "qapi/error.h"
|
||||||
|
|
||||||
/*#define DEBUG_UIC*/
|
/*#define DEBUG_UIC*/
|
||||||
|
|
||||||
|
@ -76,250 +79,40 @@ PowerPCCPU *ppc4xx_init(const char *cpu_type,
|
||||||
|
|
||||||
/*****************************************************************************/
|
/*****************************************************************************/
|
||||||
/* "Universal" Interrupt controller */
|
/* "Universal" Interrupt controller */
|
||||||
enum {
|
|
||||||
DCR_UICSR = 0x000,
|
|
||||||
DCR_UICSRS = 0x001,
|
|
||||||
DCR_UICER = 0x002,
|
|
||||||
DCR_UICCR = 0x003,
|
|
||||||
DCR_UICPR = 0x004,
|
|
||||||
DCR_UICTR = 0x005,
|
|
||||||
DCR_UICMSR = 0x006,
|
|
||||||
DCR_UICVR = 0x007,
|
|
||||||
DCR_UICVCR = 0x008,
|
|
||||||
DCR_UICMAX = 0x009,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UIC_MAX_IRQ 32
|
|
||||||
typedef struct ppcuic_t ppcuic_t;
|
|
||||||
struct ppcuic_t {
|
|
||||||
uint32_t dcr_base;
|
|
||||||
int use_vectors;
|
|
||||||
uint32_t level; /* Remembers the state of level-triggered interrupts. */
|
|
||||||
uint32_t uicsr; /* Status register */
|
|
||||||
uint32_t uicer; /* Enable register */
|
|
||||||
uint32_t uiccr; /* Critical register */
|
|
||||||
uint32_t uicpr; /* Polarity register */
|
|
||||||
uint32_t uictr; /* Triggering register */
|
|
||||||
uint32_t uicvcr; /* Vector configuration register */
|
|
||||||
uint32_t uicvr;
|
|
||||||
qemu_irq *irqs;
|
|
||||||
};
|
|
||||||
|
|
||||||
static void ppcuic_trigger_irq(ppcuic_t *uic)
|
|
||||||
{
|
|
||||||
uint32_t ir, cr;
|
|
||||||
int start, end, inc, i;
|
|
||||||
|
|
||||||
/* Trigger interrupt if any is pending */
|
|
||||||
ir = uic->uicsr & uic->uicer & (~uic->uiccr);
|
|
||||||
cr = uic->uicsr & uic->uicer & uic->uiccr;
|
|
||||||
LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
|
|
||||||
" uiccr %08" PRIx32 "\n"
|
|
||||||
" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
|
|
||||||
__func__, uic->uicsr, uic->uicer, uic->uiccr,
|
|
||||||
uic->uicsr & uic->uicer, ir, cr);
|
|
||||||
if (ir != 0x0000000) {
|
|
||||||
LOG_UIC("Raise UIC interrupt\n");
|
|
||||||
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
|
|
||||||
} else {
|
|
||||||
LOG_UIC("Lower UIC interrupt\n");
|
|
||||||
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
|
|
||||||
}
|
|
||||||
/* Trigger critical interrupt if any is pending and update vector */
|
|
||||||
if (cr != 0x0000000) {
|
|
||||||
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
|
|
||||||
if (uic->use_vectors) {
|
|
||||||
/* Compute critical IRQ vector */
|
|
||||||
if (uic->uicvcr & 1) {
|
|
||||||
start = 31;
|
|
||||||
end = 0;
|
|
||||||
inc = -1;
|
|
||||||
} else {
|
|
||||||
start = 0;
|
|
||||||
end = 31;
|
|
||||||
inc = 1;
|
|
||||||
}
|
|
||||||
uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
|
|
||||||
for (i = start; i <= end; i += inc) {
|
|
||||||
if (cr & (1 << i)) {
|
|
||||||
uic->uicvr += (i - start) * 512 * inc;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
LOG_UIC("Raise UIC critical interrupt - "
|
|
||||||
"vector %08" PRIx32 "\n", uic->uicvr);
|
|
||||||
} else {
|
|
||||||
LOG_UIC("Lower UIC critical interrupt\n");
|
|
||||||
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
|
|
||||||
uic->uicvr = 0x00000000;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ppcuic_set_irq(void *opaque, int irq_num, int level)
|
|
||||||
{
|
|
||||||
ppcuic_t *uic;
|
|
||||||
uint32_t mask, sr;
|
|
||||||
|
|
||||||
uic = opaque;
|
|
||||||
mask = 1U << (31 - irq_num);
|
|
||||||
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
|
|
||||||
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
|
|
||||||
__func__, irq_num, level,
|
|
||||||
uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
|
|
||||||
if (irq_num < 0 || irq_num > 31) {
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
sr = uic->uicsr;
|
|
||||||
|
|
||||||
/* Update status register */
|
|
||||||
if (uic->uictr & mask) {
|
|
||||||
/* Edge sensitive interrupt */
|
|
||||||
if (level == 1) {
|
|
||||||
uic->uicsr |= mask;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
/* Level sensitive interrupt */
|
|
||||||
if (level == 1) {
|
|
||||||
uic->uicsr |= mask;
|
|
||||||
uic->level |= mask;
|
|
||||||
} else {
|
|
||||||
uic->uicsr &= ~mask;
|
|
||||||
uic->level &= ~mask;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
|
|
||||||
"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
|
|
||||||
if (sr != uic->uicsr) {
|
|
||||||
ppcuic_trigger_irq(uic);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint32_t dcr_read_uic(void *opaque, int dcrn)
|
|
||||||
{
|
|
||||||
ppcuic_t *uic;
|
|
||||||
uint32_t ret;
|
|
||||||
|
|
||||||
uic = opaque;
|
|
||||||
dcrn -= uic->dcr_base;
|
|
||||||
switch (dcrn) {
|
|
||||||
case DCR_UICSR:
|
|
||||||
case DCR_UICSRS:
|
|
||||||
ret = uic->uicsr;
|
|
||||||
break;
|
|
||||||
case DCR_UICER:
|
|
||||||
ret = uic->uicer;
|
|
||||||
break;
|
|
||||||
case DCR_UICCR:
|
|
||||||
ret = uic->uiccr;
|
|
||||||
break;
|
|
||||||
case DCR_UICPR:
|
|
||||||
ret = uic->uicpr;
|
|
||||||
break;
|
|
||||||
case DCR_UICTR:
|
|
||||||
ret = uic->uictr;
|
|
||||||
break;
|
|
||||||
case DCR_UICMSR:
|
|
||||||
ret = uic->uicsr & uic->uicer;
|
|
||||||
break;
|
|
||||||
case DCR_UICVR:
|
|
||||||
if (!uic->use_vectors) {
|
|
||||||
goto no_read;
|
|
||||||
}
|
|
||||||
ret = uic->uicvr;
|
|
||||||
break;
|
|
||||||
case DCR_UICVCR:
|
|
||||||
if (!uic->use_vectors) {
|
|
||||||
goto no_read;
|
|
||||||
}
|
|
||||||
ret = uic->uicvcr;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
no_read:
|
|
||||||
ret = 0x00000000;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void dcr_write_uic(void *opaque, int dcrn, uint32_t val)
|
|
||||||
{
|
|
||||||
ppcuic_t *uic;
|
|
||||||
|
|
||||||
uic = opaque;
|
|
||||||
dcrn -= uic->dcr_base;
|
|
||||||
LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
|
|
||||||
switch (dcrn) {
|
|
||||||
case DCR_UICSR:
|
|
||||||
uic->uicsr &= ~val;
|
|
||||||
uic->uicsr |= uic->level;
|
|
||||||
ppcuic_trigger_irq(uic);
|
|
||||||
break;
|
|
||||||
case DCR_UICSRS:
|
|
||||||
uic->uicsr |= val;
|
|
||||||
ppcuic_trigger_irq(uic);
|
|
||||||
break;
|
|
||||||
case DCR_UICER:
|
|
||||||
uic->uicer = val;
|
|
||||||
ppcuic_trigger_irq(uic);
|
|
||||||
break;
|
|
||||||
case DCR_UICCR:
|
|
||||||
uic->uiccr = val;
|
|
||||||
ppcuic_trigger_irq(uic);
|
|
||||||
break;
|
|
||||||
case DCR_UICPR:
|
|
||||||
uic->uicpr = val;
|
|
||||||
break;
|
|
||||||
case DCR_UICTR:
|
|
||||||
uic->uictr = val;
|
|
||||||
ppcuic_trigger_irq(uic);
|
|
||||||
break;
|
|
||||||
case DCR_UICMSR:
|
|
||||||
break;
|
|
||||||
case DCR_UICVR:
|
|
||||||
break;
|
|
||||||
case DCR_UICVCR:
|
|
||||||
uic->uicvcr = val & 0xFFFFFFFD;
|
|
||||||
ppcuic_trigger_irq(uic);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ppcuic_reset (void *opaque)
|
|
||||||
{
|
|
||||||
ppcuic_t *uic;
|
|
||||||
|
|
||||||
uic = opaque;
|
|
||||||
uic->uiccr = 0x00000000;
|
|
||||||
uic->uicer = 0x00000000;
|
|
||||||
uic->uicpr = 0x00000000;
|
|
||||||
uic->uicsr = 0x00000000;
|
|
||||||
uic->uictr = 0x00000000;
|
|
||||||
if (uic->use_vectors) {
|
|
||||||
uic->uicvcr = 0x00000000;
|
|
||||||
uic->uicvr = 0x0000000;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
|
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
|
||||||
uint32_t dcr_base, int has_ssr, int has_vr)
|
uint32_t dcr_base, int has_ssr, int has_vr)
|
||||||
{
|
{
|
||||||
ppcuic_t *uic;
|
DeviceState *uicdev = qdev_new(TYPE_PPC_UIC);
|
||||||
|
SysBusDevice *uicsbd = SYS_BUS_DEVICE(uicdev);
|
||||||
|
qemu_irq *uic_irqs;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
uic = g_malloc0(sizeof(ppcuic_t));
|
qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base);
|
||||||
uic->dcr_base = dcr_base;
|
qdev_prop_set_bit(uicdev, "use-vectors", has_vr);
|
||||||
uic->irqs = irqs;
|
object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)),
|
||||||
if (has_vr)
|
&error_fatal);
|
||||||
uic->use_vectors = 1;
|
sysbus_realize_and_unref(uicsbd, &error_fatal);
|
||||||
for (i = 0; i < DCR_UICMAX; i++) {
|
|
||||||
ppc_dcr_register(env, dcr_base + i, uic,
|
|
||||||
&dcr_read_uic, &dcr_write_uic);
|
|
||||||
}
|
|
||||||
qemu_register_reset(ppcuic_reset, uic);
|
|
||||||
|
|
||||||
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]);
|
||||||
|
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT]);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return an allocated array of the UIC's input IRQ lines.
|
||||||
|
* This is an ugly temporary API to retain compatibility with
|
||||||
|
* the ppcuic_init() interface from the pre-QOM-conversion UIC.
|
||||||
|
* None of the callers free this array, so it is leaked -- but
|
||||||
|
* so was the array allocated by qemu_allocate_irqs() in the
|
||||||
|
* old code.
|
||||||
|
*
|
||||||
|
* The callers should just instantiate the UIC and wire it up
|
||||||
|
* themselves rather than passing qemu_irq* in and out of this function.
|
||||||
|
*/
|
||||||
|
uic_irqs = g_new0(qemu_irq, UIC_MAX_IRQ);
|
||||||
|
for (i = 0; i < UIC_MAX_IRQ; i++) {
|
||||||
|
uic_irqs[i] = qdev_get_gpio_in(uicdev, i);
|
||||||
|
}
|
||||||
|
return uic_irqs;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*****************************************************************************/
|
/*****************************************************************************/
|
||||||
|
|
73
include/hw/intc/ppc-uic.h
Normal file
73
include/hw/intc/ppc-uic.h
Normal file
|
@ -0,0 +1,73 @@
|
||||||
|
/*
|
||||||
|
* "Universal" Interrupt Controller for PowerPPC 4xx embedded processors
|
||||||
|
*
|
||||||
|
* Copyright (c) 2007 Jocelyn Mayer
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef HW_INTC_PPC_UIC_H
|
||||||
|
#define HW_INTC_PPC_UIC_H
|
||||||
|
|
||||||
|
#include "hw/sysbus.h"
|
||||||
|
#include "qom/object.h"
|
||||||
|
|
||||||
|
#define TYPE_PPC_UIC "ppc-uic"
|
||||||
|
OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* QEMU interface:
|
||||||
|
* QOM property "cpu": link to the PPC CPU
|
||||||
|
* (no default, must be set)
|
||||||
|
* QOM property "dcr-base": base of the bank of DCR registers for the UIC
|
||||||
|
* (default 0x30)
|
||||||
|
* QOM property "use-vectors": true if the UIC has vector registers
|
||||||
|
* (default true)
|
||||||
|
* unnamed GPIO inputs 0..UIC_MAX_IRQ: input IRQ lines
|
||||||
|
* sysbus IRQs:
|
||||||
|
* 0 (PPCUIC_OUTPUT_INT): output INT line to the CPU
|
||||||
|
* 1 (PPCUIC_OUTPUT_CINT): output CINT line to the CPU
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define UIC_MAX_IRQ 32
|
||||||
|
|
||||||
|
struct PPCUIC {
|
||||||
|
/*< private >*/
|
||||||
|
SysBusDevice parent_obj;
|
||||||
|
|
||||||
|
/*< public >*/
|
||||||
|
qemu_irq output_int;
|
||||||
|
qemu_irq output_cint;
|
||||||
|
|
||||||
|
/* properties */
|
||||||
|
CPUState *cpu;
|
||||||
|
uint32_t dcr_base;
|
||||||
|
bool use_vectors;
|
||||||
|
|
||||||
|
uint32_t level; /* Remembers the state of level-triggered interrupts. */
|
||||||
|
uint32_t uicsr; /* Status register */
|
||||||
|
uint32_t uicer; /* Enable register */
|
||||||
|
uint32_t uiccr; /* Critical register */
|
||||||
|
uint32_t uicpr; /* Polarity register */
|
||||||
|
uint32_t uictr; /* Triggering register */
|
||||||
|
uint32_t uicvcr; /* Vector configuration register */
|
||||||
|
uint32_t uicvr;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
Loading…
Reference in a new issue