riscv: Add helper to make NaN-boxing for FP register
The function that makes NaN-boxing when a 32-bit value is assigned to a 64-bit FP register is split out to a helper gen_nanbox_fpr(). Then it is applied in translating of the FLW instruction. Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Message-Id: <20200128003707.17028-1-ianjiang.ict@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -23,6 +23,20 @@
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return false; \
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return false; \
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} while (0)
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} while (0)
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/*
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* RISC-V requires NaN-boxing of narrower width floating
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* point values. This applies when a 32-bit value is
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* assigned to a 64-bit FP register. Thus this does not
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* apply when the RVD extension is not present.
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*/
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static void gen_nanbox_fpr(DisasContext *ctx, int regno)
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{
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if (has_ext(ctx, RVD)) {
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tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],
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MAKE_64BIT_MASK(32, 32));
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}
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}
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static bool trans_flw(DisasContext *ctx, arg_flw *a)
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static bool trans_flw(DisasContext *ctx, arg_flw *a)
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{
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{
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TCGv t0 = tcg_temp_new();
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TCGv t0 = tcg_temp_new();
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@ -32,8 +46,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
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/* RISC-V requires NaN-boxing of narrower width floating point values */
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gen_nanbox_fpr(ctx, a->rd);
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tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
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tcg_temp_free(t0);
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tcg_temp_free(t0);
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mark_fs_dirty(ctx);
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mark_fs_dirty(ctx);
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