net: cadence_gem: Implement support for 64bit descriptor addresses
Implement support for 64bit descriptor addresses. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181011021931.4249-8-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -153,6 +153,9 @@
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#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
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#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
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#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
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#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
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#define GEM_TBQPH (0x000004C8 / 4)
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#define GEM_RBQPH (0x000004D4 / 4)
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#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
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#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
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#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
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#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
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@ -832,18 +835,42 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
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return 0;
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return 0;
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}
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}
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static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
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{
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hwaddr desc_addr = 0;
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if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
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desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH];
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}
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desc_addr <<= 32;
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desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
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return desc_addr;
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}
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static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q)
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{
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return gem_get_desc_addr(s, true, q);
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}
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static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q)
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{
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return gem_get_desc_addr(s, false, q);
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}
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static void gem_get_rx_desc(CadenceGEMState *s, int q)
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static void gem_get_rx_desc(CadenceGEMState *s, int q)
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{
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{
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DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
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hwaddr desc_addr = gem_get_rx_desc_addr(s, q);
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DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr);
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/* read current descriptor */
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/* read current descriptor */
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address_space_read(&s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFIED,
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address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
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(uint8_t *)s->rx_desc[q],
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(uint8_t *)s->rx_desc[q],
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sizeof(uint32_t) * gem_get_desc_len(s, true));
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sizeof(uint32_t) * gem_get_desc_len(s, true));
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/* Descriptor owned by software ? */
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/* Descriptor owned by software ? */
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if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
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if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
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DB_PRINT("descriptor 0x%x owned by sw.\n",
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DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
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(unsigned)s->rx_desc_addr[q]);
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s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
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s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
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s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
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s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
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/* Handle interrupt consequences */
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/* Handle interrupt consequences */
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@ -947,6 +974,8 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
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q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
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q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
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while (bytes_to_copy) {
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while (bytes_to_copy) {
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hwaddr desc_addr;
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/* Do nothing if receive is not enabled. */
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/* Do nothing if receive is not enabled. */
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if (!gem_can_receive(nc)) {
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if (!gem_can_receive(nc)) {
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assert(!first_desc);
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assert(!first_desc);
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@ -994,7 +1023,8 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
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}
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}
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/* Descriptor write-back. */
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/* Descriptor write-back. */
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address_space_write(&s->dma_as, s->rx_desc_addr[q],
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desc_addr = gem_get_rx_desc_addr(s, q);
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address_space_write(&s->dma_as, desc_addr,
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MEMTXATTRS_UNSPECIFIED,
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MEMTXATTRS_UNSPECIFIED,
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(uint8_t *)s->rx_desc[q],
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(uint8_t *)s->rx_desc[q],
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sizeof(uint32_t) * gem_get_desc_len(s, true));
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sizeof(uint32_t) * gem_get_desc_len(s, true));
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@ -1098,7 +1128,7 @@ static void gem_transmit(CadenceGEMState *s)
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for (q = s->num_priority_queues - 1; q >= 0; q--) {
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for (q = s->num_priority_queues - 1; q >= 0; q--) {
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/* read current descriptor */
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/* read current descriptor */
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packet_desc_addr = s->tx_desc_addr[q];
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packet_desc_addr = gem_get_tx_desc_addr(s, q);
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DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
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DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
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address_space_read(&s->dma_as, packet_desc_addr,
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address_space_read(&s->dma_as, packet_desc_addr,
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@ -1144,16 +1174,17 @@ static void gem_transmit(CadenceGEMState *s)
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/* Last descriptor for this packet; hand the whole thing off */
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/* Last descriptor for this packet; hand the whole thing off */
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if (tx_desc_get_last(desc)) {
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if (tx_desc_get_last(desc)) {
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uint32_t desc_first[DESC_MAX_NUM_WORDS];
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uint32_t desc_first[DESC_MAX_NUM_WORDS];
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hwaddr desc_addr = gem_get_tx_desc_addr(s, q);
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/* Modify the 1st descriptor of this packet to be owned by
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/* Modify the 1st descriptor of this packet to be owned by
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* the processor.
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* the processor.
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*/
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*/
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address_space_read(&s->dma_as, s->tx_desc_addr[q],
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address_space_read(&s->dma_as, desc_addr,
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MEMTXATTRS_UNSPECIFIED,
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MEMTXATTRS_UNSPECIFIED,
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(uint8_t *)desc_first,
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(uint8_t *)desc_first,
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sizeof(desc_first));
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sizeof(desc_first));
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tx_desc_set_used(desc_first);
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tx_desc_set_used(desc_first);
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address_space_write(&s->dma_as, s->tx_desc_addr[q],
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address_space_write(&s->dma_as, desc_addr,
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MEMTXATTRS_UNSPECIFIED,
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MEMTXATTRS_UNSPECIFIED,
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(uint8_t *)desc_first,
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(uint8_t *)desc_first,
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sizeof(desc_first));
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sizeof(desc_first));
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