target-arm: A64: Add floating-point<->fixed-point instructions
This patch adds emulation for the instruction group labeled "Floating-point <-> fixed-point conversions" in the ARM ARM. Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU (scalar, fixed-point). Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, rebased, updated to new infrastructure. Applied bug fixes from Michael Matz and Janne Grunau.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: significant cleanup] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -4035,6 +4035,19 @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
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#undef VFP_CONV_FIX_FLOAT
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#undef VFP_CONV_FLOAT_FIX_ROUND
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/* Set the current fp rounding mode and return the old one.
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* The argument is a softfloat float_round_ value.
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*/
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uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
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{
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float_status *fp_status = &env->vfp.fp_status;
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uint32_t prev_rmode = get_float_rounding_mode(fp_status);
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set_float_rounding_mode(rmode, fp_status);
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return prev_rmode;
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}
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/* Half precision conversions. */
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static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
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{
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@ -148,6 +148,8 @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
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DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
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DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
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DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env)
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DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env)
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DEF_HELPER_2(vfp_fcvt_f32_to_f16, i32, f32, env)
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DEF_HELPER_2(neon_fcvt_f16_to_f32, f32, i32, env)
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@ -3186,6 +3186,34 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
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}
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}
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/* Convert ARM rounding mode to softfloat */
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static inline int arm_rmode_to_sf(int rmode)
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{
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switch (rmode) {
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case FPROUNDING_TIEAWAY:
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rmode = float_round_ties_away;
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break;
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case FPROUNDING_ODD:
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/* FIXME: add support for TIEAWAY and ODD */
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qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
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rmode);
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case FPROUNDING_TIEEVEN:
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default:
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rmode = float_round_nearest_even;
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break;
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case FPROUNDING_POSINF:
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rmode = float_round_up;
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break;
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case FPROUNDING_NEGINF:
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rmode = float_round_down;
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break;
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case FPROUNDING_ZERO:
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rmode = float_round_to_zero;
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break;
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}
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return rmode;
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}
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static void handle_fp_compare(DisasContext *s, bool is_double,
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unsigned int rn, unsigned int rm,
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bool cmp_with_zero, bool signal_all_nans)
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@ -3651,6 +3679,132 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_res);
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}
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/* Handle floating point <=> fixed point conversions. Note that we can
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* also deal with fp <=> integer conversions as a special case (scale == 64)
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* OPTME: consider handling that special case specially or at least skipping
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* the call to scalbn in the helpers for zero shifts.
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*/
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static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
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bool itof, int rmode, int scale, int sf, int type)
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{
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bool is_signed = !(opcode & 1);
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bool is_double = type;
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TCGv_ptr tcg_fpstatus;
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TCGv_i32 tcg_shift;
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tcg_fpstatus = get_fpstatus_ptr();
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tcg_shift = tcg_const_i32(64 - scale);
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if (itof) {
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TCGv_i64 tcg_int = cpu_reg(s, rn);
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if (!sf) {
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TCGv_i64 tcg_extend = new_tmp_a64(s);
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if (is_signed) {
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tcg_gen_ext32s_i64(tcg_extend, tcg_int);
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} else {
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tcg_gen_ext32u_i64(tcg_extend, tcg_int);
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}
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tcg_int = tcg_extend;
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}
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if (is_double) {
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TCGv_i64 tcg_double = tcg_temp_new_i64();
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if (is_signed) {
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gen_helper_vfp_sqtod(tcg_double, tcg_int,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_uqtod(tcg_double, tcg_int,
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tcg_shift, tcg_fpstatus);
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}
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write_fp_dreg(s, rd, tcg_double);
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tcg_temp_free_i64(tcg_double);
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} else {
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TCGv_i32 tcg_single = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_sqtos(tcg_single, tcg_int,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_uqtos(tcg_single, tcg_int,
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tcg_shift, tcg_fpstatus);
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}
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write_fp_sreg(s, rd, tcg_single);
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tcg_temp_free_i32(tcg_single);
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}
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} else {
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TCGv_i64 tcg_int = cpu_reg(s, rd);
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TCGv_i32 tcg_rmode;
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if (extract32(opcode, 2, 1)) {
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/* There are too many rounding modes to all fit into rmode,
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* so FCVTA[US] is a special case.
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*/
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rmode = FPROUNDING_TIEAWAY;
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}
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tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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if (is_double) {
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TCGv_i64 tcg_double = read_fp_dreg(s, rn);
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if (is_signed) {
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if (!sf) {
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gen_helper_vfp_tosld(tcg_int, tcg_double,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_tosqd(tcg_int, tcg_double,
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tcg_shift, tcg_fpstatus);
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}
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} else {
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if (!sf) {
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gen_helper_vfp_tould(tcg_int, tcg_double,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_touqd(tcg_int, tcg_double,
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tcg_shift, tcg_fpstatus);
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}
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}
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tcg_temp_free_i64(tcg_double);
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} else {
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TCGv_i32 tcg_single = read_fp_sreg(s, rn);
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if (sf) {
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if (is_signed) {
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gen_helper_vfp_tosqs(tcg_int, tcg_single,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_touqs(tcg_int, tcg_single,
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tcg_shift, tcg_fpstatus);
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}
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} else {
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TCGv_i32 tcg_dest = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_tosls(tcg_dest, tcg_single,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_touls(tcg_dest, tcg_single,
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tcg_shift, tcg_fpstatus);
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}
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tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
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tcg_temp_free_i32(tcg_dest);
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}
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tcg_temp_free_i32(tcg_single);
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}
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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tcg_temp_free_i32(tcg_rmode);
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if (!sf) {
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tcg_gen_ext32u_i64(tcg_int, tcg_int);
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}
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}
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tcg_temp_free_ptr(tcg_fpstatus);
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tcg_temp_free_i32(tcg_shift);
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}
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/* C3.6.29 Floating point <-> fixed point conversions
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* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
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* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
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@ -3659,7 +3813,37 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
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*/
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static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int scale = extract32(insn, 10, 6);
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int opcode = extract32(insn, 16, 3);
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int rmode = extract32(insn, 19, 2);
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int type = extract32(insn, 22, 2);
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bool sbit = extract32(insn, 29, 1);
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bool sf = extract32(insn, 31, 1);
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bool itof;
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if (sbit || (type > 1)
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|| (!sf && scale < 32)) {
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unallocated_encoding(s);
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return;
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}
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switch ((rmode << 3) | opcode) {
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case 0x2: /* SCVTF */
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case 0x3: /* UCVTF */
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itof = true;
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break;
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case 0x18: /* FCVTZS */
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case 0x19: /* FCVTZU */
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itof = false;
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type);
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}
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static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
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