virtio, pci: fixes
More fixes missed in the previous pull request. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJYyfidAAoJECgfDbjSjVRp1yYIAKC52EwDVcJxL2CEGncCQTVT i9x04TYmzLOO+dERsO7Z+jphoB1cxpVxZVrvG5wfZo07gcGheNk524ABM2c9tNqa 7OZFcdBmN/l5C9ynL6aCdgu/bns5sEMUXf3By3l8iWKupc1C8URWGrfMVypFDumZ AOSD/4bbvXxZlZjOENq5LsRHYU68KBK07C1fDRJA7b7ChXHS6qefeq6fbOvI9zJ7 24MltJMsNS36l//namD2HFPnO1eD3HXc57yBn5QBTTn5FERIghxYSsluAY7irKMp UurF1D0pUL1sU2fjaLwFRBJL15tz6syjYOkna9cGmOT8m1D7CYnKjCRErxtqAmE= =4pMp -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging virtio, pci: fixes More fixes missed in the previous pull request. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Thu 16 Mar 2017 02:29:49 GMT # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio-serial-bus: Delete timer from list before free it hw/virtio: fix Power Management Control Register for PCI Express virtio devices hw/virtio: fix Link Control Register for PCI Express virtio devices hw/virtio: fix error enabling flags in Device Control register hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
3716fba3f5
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dtc
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@ -1 +1 @@
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Subproject commit 558cd81bdd432769b59bff01240c44f82cfb1a9d
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Subproject commit 65cc4d2748a2c2e6f27f1cf39e07a5dbabd80ebf
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@ -724,6 +724,7 @@ static void virtio_serial_post_load_timer_cb(void *opaque)
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}
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}
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g_free(s->post_load->connected);
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timer_del(s->post_load->timer);
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timer_free(s->post_load->timer);
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g_free(s->post_load);
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s->post_load = NULL;
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@ -64,6 +64,8 @@ static Property pci_props[] = {
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QEMU_PCI_CAP_SERR_BITNR, true),
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DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
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QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
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DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
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QEMU_PCIE_EXTCAP_INIT_BITNR, true),
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DEFINE_PROP_END_OF_LIST()
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};
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@ -109,6 +109,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
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pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
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if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
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/* read-only to behave like a 'NULL' Extended Capability Header */
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pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
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}
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return pos;
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}
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@ -217,6 +223,20 @@ void pcie_cap_deverr_reset(PCIDevice *dev)
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PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
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}
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void pcie_cap_lnkctl_init(PCIDevice *dev)
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{
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uint32_t pos = dev->exp.exp_cap;
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pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
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}
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void pcie_cap_lnkctl_reset(PCIDevice *dev)
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{
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uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;
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pci_long_test_and_clear_mask(lnkctl,
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PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
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}
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static void hotplug_event_update_event_status(PCIDevice *dev)
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{
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uint32_t pos = dev->exp.exp_cap;
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@ -1812,6 +1812,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
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pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF);
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assert(pos > 0);
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pci_dev->exp.pm_cap = pos;
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/*
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* Indicates that this function complies with revision 1.2 of the
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@ -1819,6 +1820,22 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
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*/
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pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
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if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
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/* Init error enabling flags */
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pcie_cap_deverr_init(pci_dev);
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}
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if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {
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/* Init Link Control Register */
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pcie_cap_lnkctl_init(pci_dev);
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}
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if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
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/* Init Power Management Control Register */
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pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
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PCI_PM_CTRL_STATE_MASK);
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}
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if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
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pcie_ats_init(pci_dev, 256);
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}
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@ -1849,6 +1866,7 @@ static void virtio_pci_reset(DeviceState *qdev)
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{
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VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
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VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
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PCIDevice *dev = PCI_DEVICE(qdev);
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int i;
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virtio_pci_stop_ioeventfd(proxy);
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@ -1862,6 +1880,13 @@ static void virtio_pci_reset(DeviceState *qdev)
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proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0;
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proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0;
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}
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if (pci_is_express(dev)) {
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pcie_cap_deverr_reset(dev);
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pcie_cap_lnkctl_reset(dev);
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pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
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}
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}
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static Property virtio_pci_properties[] = {
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@ -1882,6 +1907,12 @@ static Property virtio_pci_properties[] = {
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ignore_backend_features, false),
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DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
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VIRTIO_PCI_FLAG_ATS_BIT, false),
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DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
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VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
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DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
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VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
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DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
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VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -73,6 +73,9 @@ enum {
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VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT,
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VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT,
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VIRTIO_PCI_FLAG_ATS_BIT,
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VIRTIO_PCI_FLAG_INIT_DEVERR_BIT,
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VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
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VIRTIO_PCI_FLAG_INIT_PM_BIT,
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};
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/* Need to activate work-arounds for buggy guests at vmstate load. */
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@ -100,6 +103,15 @@ enum {
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/* address space translation service */
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#define VIRTIO_PCI_FLAG_ATS (1 << VIRTIO_PCI_FLAG_ATS_BIT)
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/* Init error enabling flags */
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#define VIRTIO_PCI_FLAG_INIT_DEVERR (1 << VIRTIO_PCI_FLAG_INIT_DEVERR_BIT)
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/* Init Link Control register */
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#define VIRTIO_PCI_FLAG_INIT_LNKCTL (1 << VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT)
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/* Init Power Management */
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#define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
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typedef struct {
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MSIMessage msg;
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int virq;
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@ -18,6 +18,22 @@
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.driver = "pci-bridge",\
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.property = "shpc",\
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.value = "on",\
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},{\
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.driver = TYPE_PCI_DEVICE,\
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.property = "x-pcie-extcap-init",\
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.value = "off",\
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},{\
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.driver = "virtio-pci",\
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.property = "x-pcie-deverr-init",\
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.value = "off",\
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},{\
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.driver = "virtio-pci",\
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.property = "x-pcie-lnkctl-init",\
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.value = "off",\
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},{\
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.driver = "virtio-pci",\
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.property = "x-pcie-pm-init",\
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.value = "off",\
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},
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#define HW_COMPAT_2_7 \
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@ -183,6 +183,8 @@ enum {
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/* Link active status in endpoint capability is always set */
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#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
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QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
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#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
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QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
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};
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#define TYPE_PCI_DEVICE "pci-device"
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@ -63,6 +63,8 @@ typedef enum {
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struct PCIExpressDevice {
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/* Offset of express capability in config space */
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uint8_t exp_cap;
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/* Offset of Power Management capability in config space */
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uint8_t pm_cap;
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/* SLOT */
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bool hpev_notified; /* Logical AND of conditions for hot plug event.
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@ -96,6 +98,9 @@ uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
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void pcie_cap_deverr_init(PCIDevice *dev);
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void pcie_cap_deverr_reset(PCIDevice *dev);
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void pcie_cap_lnkctl_init(PCIDevice *dev);
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void pcie_cap_lnkctl_reset(PCIDevice *dev);
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void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
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void pcie_cap_slot_reset(PCIDevice *dev);
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void pcie_cap_slot_write_config(PCIDevice *dev,
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