tcg-sparc: Use defines for temporaries.
And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
1fd9594665
commit
375816f84b
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@ -59,8 +59,12 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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};
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};
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#endif
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#endif
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/* Define some temporary registers. T2 is used for constant generation. */
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#define TCG_REG_T1 TCG_REG_G1
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#define TCG_REG_T2 TCG_REG_O7
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#ifdef CONFIG_USE_GUEST_BASE
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#ifdef CONFIG_USE_GUEST_BASE
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# define TCG_GUEST_BASE_REG TCG_REG_I3
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# define TCG_GUEST_BASE_REG TCG_REG_I5
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#else
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#else
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# define TCG_GUEST_BASE_REG TCG_REG_G0
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# define TCG_GUEST_BASE_REG TCG_REG_G0
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#endif
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#endif
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@ -79,6 +83,7 @@ static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_I2,
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TCG_REG_I2,
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TCG_REG_I3,
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TCG_REG_I3,
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TCG_REG_I4,
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TCG_REG_I4,
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TCG_REG_I5,
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};
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};
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static const int tcg_target_call_iarg_regs[6] = {
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static const int tcg_target_call_iarg_regs[6] = {
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@ -366,10 +371,10 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
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tcg_out_sethi(s, ret, ~arg);
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tcg_out_sethi(s, ret, ~arg);
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tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
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tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
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} else {
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} else {
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tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
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tcg_out_movi_imm32(s, ret, arg >> (TCG_TARGET_REG_BITS / 2));
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tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
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tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
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tcg_out_movi_imm32(s, ret, arg);
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tcg_out_movi_imm32(s, TCG_REG_T2, arg);
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tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
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tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR);
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}
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}
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}
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}
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@ -386,8 +391,8 @@ static inline void tcg_out_ldst(TCGContext *s, int ret, int addr,
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tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
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tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
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INSN_IMM13(offset));
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INSN_IMM13(offset));
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} else {
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} else {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset);
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tcg_out_ldst_rr(s, ret, addr, TCG_REG_I5, op);
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tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op);
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}
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}
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}
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}
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@ -428,8 +433,8 @@ static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
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if (check_fit_tl(val, 13))
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if (check_fit_tl(val, 13))
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tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
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tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
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else {
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else {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, val);
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tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
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tcg_out_arith(s, reg, reg, TCG_REG_T1, ARITH_ADD);
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}
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}
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}
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}
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}
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}
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@ -441,8 +446,8 @@ static inline void tcg_out_andi(TCGContext *s, int rd, int rs,
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if (check_fit_tl(val, 13))
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if (check_fit_tl(val, 13))
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tcg_out_arithi(s, rd, rs, val, ARITH_AND);
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tcg_out_arithi(s, rd, rs, val, ARITH_AND);
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else {
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else {
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T1, val);
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tcg_out_arith(s, rd, rs, TCG_REG_I5, ARITH_AND);
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tcg_out_arith(s, rd, rs, TCG_REG_T1, ARITH_AND);
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}
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}
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}
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}
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}
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}
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@ -454,8 +459,8 @@ static void tcg_out_div32(TCGContext *s, int rd, int rs1,
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if (uns) {
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if (uns) {
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tcg_out_sety(s, TCG_REG_G0);
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tcg_out_sety(s, TCG_REG_G0);
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} else {
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} else {
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tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
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tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA);
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tcg_out_sety(s, TCG_REG_I5);
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tcg_out_sety(s, TCG_REG_T1);
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}
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}
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tcg_out_arithc(s, rd, rs1, val2, val2const,
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tcg_out_arithc(s, rd, rs1, val2, val2const,
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@ -601,8 +606,8 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
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case TCG_COND_GTU:
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case TCG_COND_GTU:
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case TCG_COND_GEU:
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case TCG_COND_GEU:
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if (c2const && c2 != 0) {
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if (c2const && c2 != 0) {
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tcg_out_movi_imm13(s, TCG_REG_I5, c2);
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tcg_out_movi_imm13(s, TCG_REG_T1, c2);
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c2 = TCG_REG_I5;
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c2 = TCG_REG_T1;
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}
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}
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t = c1, c1 = c2, c2 = t, c2const = 0;
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t = c1, c1 = c2, c2 = t, c2const = 0;
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cond = tcg_swap_cond(cond);
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cond = tcg_swap_cond(cond);
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@ -649,15 +654,15 @@ static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
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switch (cond) {
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switch (cond) {
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case TCG_COND_EQ:
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case TCG_COND_EQ:
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tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
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tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_T1, al, bl, blconst);
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tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
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tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
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tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
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tcg_out_arith(s, ret, ret, TCG_REG_T1, ARITH_AND);
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break;
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break;
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case TCG_COND_NE:
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case TCG_COND_NE:
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tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
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tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_T1, al, al, blconst);
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tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
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tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
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tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
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tcg_out_arith(s, ret, ret, TCG_REG_T1, ARITH_OR);
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break;
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break;
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default:
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default:
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@ -935,8 +940,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
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#else
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#else
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addr_reg = args[addrlo_idx];
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addr_reg = args[addrlo_idx];
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if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
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if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
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tcg_out_arithi(s, TCG_REG_I5, addr_reg, 0, SHIFT_SRL);
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tcg_out_arithi(s, TCG_REG_T1, addr_reg, 0, SHIFT_SRL);
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addr_reg = TCG_REG_I5;
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addr_reg = TCG_REG_T1;
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}
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}
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if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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int reg64 = (datalo < 16 ? datalo : TCG_REG_O0);
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int reg64 = (datalo < 16 ? datalo : TCG_REG_O0);
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@ -979,12 +984,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
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offsetof(CPUTLBEntry, addr_write));
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offsetof(CPUTLBEntry, addr_write));
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if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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/* Reconstruct the full 64-bit value in %g1, using %o2 as temp. */
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/* Reconstruct the full 64-bit value. */
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/* ??? Redefine the temps from %i4/%i5 so that we have a o/g temp. */
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tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL);
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tcg_out_arithi(s, TCG_REG_G1, datalo, 0, SHIFT_SRL);
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tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
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tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
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tcg_out_arith(s, TCG_REG_G1, TCG_REG_G1, TCG_REG_O2, ARITH_OR);
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tcg_out_arith(s, TCG_REG_O2, TCG_REG_T1, TCG_REG_O2, ARITH_OR);
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datalo = TCG_REG_G1;
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datalo = TCG_REG_O2;
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}
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}
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/* The fast path is exactly one insn. Thus we can perform the entire
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/* The fast path is exactly one insn. Thus we can perform the entire
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@ -1024,16 +1028,14 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
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#else
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#else
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addr_reg = args[addrlo_idx];
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addr_reg = args[addrlo_idx];
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if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
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if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
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tcg_out_arithi(s, TCG_REG_I5, addr_reg, 0, SHIFT_SRL);
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tcg_out_arithi(s, TCG_REG_T1, addr_reg, 0, SHIFT_SRL);
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addr_reg = TCG_REG_I5;
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addr_reg = TCG_REG_T1;
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}
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}
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if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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/* Reconstruct the full 64-bit value in %g1, using %o2 as temp. */
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tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL);
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/* ??? Redefine the temps from %i4/%i5 so that we have a o/g temp. */
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tcg_out_arithi(s, TCG_REG_G1, datalo, 0, SHIFT_SRL);
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tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
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tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
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tcg_out_arith(s, TCG_REG_G1, TCG_REG_G1, TCG_REG_O2, ARITH_OR);
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tcg_out_arith(s, TCG_REG_O2, TCG_REG_T1, TCG_REG_O2, ARITH_OR);
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datalo = TCG_REG_G1;
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datalo = TCG_REG_O2;
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}
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}
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tcg_out_ldst_rr(s, datalo, addr_reg,
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tcg_out_ldst_rr(s, datalo, addr_reg,
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(GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
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(GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
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@ -1057,28 +1059,29 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_goto_tb:
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case INDEX_op_goto_tb:
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if (s->tb_jmp_offset) {
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if (s->tb_jmp_offset) {
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/* direct jump method */
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/* direct jump method */
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tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
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tcg_out_sethi(s, TCG_REG_T1, args[0] & 0xffffe000);
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_T1) |
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INSN_IMM13((args[0] & 0x1fff)));
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INSN_IMM13((args[0] & 0x1fff)));
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s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
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s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
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} else {
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} else {
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/* indirect jump method */
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/* indirect jump method */
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tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
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tcg_out_ld_ptr(s, TCG_REG_T1,
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
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(tcg_target_long)(s->tb_next + args[0]));
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_T1) |
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INSN_RS2(TCG_REG_G0));
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INSN_RS2(TCG_REG_G0));
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}
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}
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tcg_out_nop(s);
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tcg_out_nop(s);
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s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
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s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
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break;
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break;
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case INDEX_op_call:
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case INDEX_op_call:
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if (const_args[0])
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if (const_args[0]) {
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tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
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tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
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- (tcg_target_ulong)s->code_ptr) >> 2)
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- (tcg_target_ulong)s->code_ptr) >> 2)
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& 0x3fffffff));
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& 0x3fffffff));
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else {
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} else {
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tcg_out_ld_ptr(s, TCG_REG_I5,
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tcg_out_ld_ptr(s, TCG_REG_T1,
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(tcg_target_long)(s->tb_next + args[0]));
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(tcg_target_long)(s->tb_next + args[0]));
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_T1) |
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INSN_RS2(TCG_REG_G0));
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INSN_RS2(TCG_REG_G0));
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}
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}
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/* delay slot */
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/* delay slot */
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@ -1184,11 +1187,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_rem_i32:
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case INDEX_op_rem_i32:
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case INDEX_op_remu_i32:
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case INDEX_op_remu_i32:
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tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
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tcg_out_div32(s, TCG_REG_T1, args[1], args[2], const_args[2],
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opc == INDEX_op_remu_i32);
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opc == INDEX_op_remu_i32);
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tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
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tcg_out_arithc(s, TCG_REG_T1, TCG_REG_T1, args[2], const_args[2],
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ARITH_UMUL);
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ARITH_UMUL);
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tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
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tcg_out_arith(s, args[0], args[1], TCG_REG_T1, ARITH_SUB);
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break;
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break;
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case INDEX_op_brcond_i32:
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case INDEX_op_brcond_i32:
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@ -1305,11 +1308,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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goto gen_arith;
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goto gen_arith;
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case INDEX_op_rem_i64:
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case INDEX_op_rem_i64:
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case INDEX_op_remu_i64:
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case INDEX_op_remu_i64:
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tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
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tcg_out_arithc(s, TCG_REG_T1, args[1], args[2], const_args[2],
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opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
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opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
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tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
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tcg_out_arithc(s, TCG_REG_T1, TCG_REG_T1, args[2], const_args[2],
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ARITH_MULX);
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ARITH_MULX);
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tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
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tcg_out_arith(s, args[0], args[1], TCG_REG_T1, ARITH_SUB);
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break;
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break;
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case INDEX_op_ext32s_i64:
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case INDEX_op_ext32s_i64:
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if (const_args[1]) {
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if (const_args[1]) {
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@ -1507,15 +1510,15 @@ static void tcg_target_init(TCGContext *s)
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(1 << TCG_REG_O7));
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(1 << TCG_REG_O7));
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tcg_regset_clear(s->reserved_regs);
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tcg_regset_clear(s->reserved_regs);
|
||||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */
|
||||||
#if TCG_TARGET_REG_BITS == 64
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */
|
||||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */
|
||||||
#endif
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */
|
||||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */
|
||||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */
|
||||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
|
||||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
|
||||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
|
|
||||||
tcg_add_target_add_op_defs(sparc_op_defs);
|
tcg_add_target_add_op_defs(sparc_op_defs);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue