target-ppc: add vmul10[u,eu,cu,ecu]q instructions
vmul10uq : Vector Multiply-by-10 Unsigned Quadword VX-form vmul10euq : Vector Multiply-by-10 Extended Unsigned Quadword VX-form vmul10cuq : Vector Multiply-by-10 & write Carry Unsigned Quadword VX-form vmul10ecuq: Vector Multiply-by-10 Extended & write Carry Unsigned Quadword VX-form Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [ Add GEN_VXFORM_DUAL_EXT with invalid bit mask ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -182,6 +182,52 @@ static void gen_mtvscr(DisasContext *ctx)
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tcg_temp_free_ptr(p);
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}
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#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv_i64 t0 = tcg_temp_new_i64(); \
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TCGv_i64 t1 = tcg_temp_new_i64(); \
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TCGv_i64 t2 = tcg_temp_new_i64(); \
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TCGv_i64 ten, z; \
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\
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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} \
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\
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ten = tcg_const_i64(10); \
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z = tcg_const_i64(0); \
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\
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if (add_cin) { \
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tcg_gen_mulu2_i64(t0, t1, cpu_avrl[rA(ctx->opcode)], ten); \
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tcg_gen_andi_i64(t2, cpu_avrl[rB(ctx->opcode)], 0xF); \
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tcg_gen_add2_i64(cpu_avrl[rD(ctx->opcode)], t2, t0, t1, t2, z); \
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} else { \
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tcg_gen_mulu2_i64(cpu_avrl[rD(ctx->opcode)], t2, \
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cpu_avrl[rA(ctx->opcode)], ten); \
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} \
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\
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if (ret_carry) { \
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tcg_gen_mulu2_i64(t0, t1, cpu_avrh[rA(ctx->opcode)], ten); \
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tcg_gen_add2_i64(t0, cpu_avrl[rD(ctx->opcode)], t0, t1, t2, z); \
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tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); \
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} else { \
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tcg_gen_mul_i64(t0, cpu_avrh[rA(ctx->opcode)], ten); \
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tcg_gen_add_i64(cpu_avrh[rD(ctx->opcode)], t0, t2); \
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} \
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\
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tcg_temp_free_i64(t0); \
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tcg_temp_free_i64(t1); \
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tcg_temp_free_i64(t2); \
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tcg_temp_free_i64(ten); \
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tcg_temp_free_i64(z); \
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} \
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GEN_VX_VMUL10(vmul10uq, 0, 0);
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GEN_VX_VMUL10(vmul10euq, 1, 0);
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GEN_VX_VMUL10(vmul10cuq, 0, 1);
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GEN_VX_VMUL10(vmul10ecuq, 1, 1);
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/* Logical operations */
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#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
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static void glue(gen_, name)(DisasContext *ctx) \
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@ -276,8 +322,30 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
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} \
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}
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/* Adds support to provide invalid mask */
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#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
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name1, flg1, flg2_1, inval1) \
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static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
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{ \
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if ((Rc(ctx->opcode) == 0) && \
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((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
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!(ctx->opcode & inval0)) { \
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gen_##name0(ctx); \
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} else if ((Rc(ctx->opcode) == 1) && \
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((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
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!(ctx->opcode & inval1)) { \
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gen_##name1(ctx); \
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} else { \
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
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} \
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}
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GEN_VXFORM(vaddubm, 0, 0);
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GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
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vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
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GEN_VXFORM(vadduhm, 0, 1);
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GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
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vmul10ecuq, PPC_NONE, PPC2_ISA300)
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GEN_VXFORM(vadduwm, 0, 2);
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GEN_VXFORM(vaddudm, 0, 3);
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GEN_VXFORM(vsububm, 0, 16);
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@ -390,7 +458,11 @@ GEN_VXFORM(vsro, 6, 17);
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GEN_VXFORM(vaddcuw, 0, 6);
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GEN_VXFORM(vsubcuw, 0, 22);
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GEN_VXFORM_ENV(vaddubs, 0, 8);
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GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
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vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
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GEN_VXFORM_ENV(vadduhs, 0, 9);
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GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
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vmul10euq, PPC_NONE, PPC2_ISA300)
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GEN_VXFORM_ENV(vadduws, 0, 10);
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GEN_VXFORM_ENV(vaddsbs, 0, 12);
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GEN_VXFORM_ENV(vaddshs, 0, 13);
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@ -55,8 +55,8 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
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GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
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GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
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GEN_VXFORM(vaddubm, 0, 0),
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GEN_VXFORM(vadduhm, 0, 1),
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GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM(vadduwm, 0, 2),
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GEN_VXFORM_207(vaddudm, 0, 3),
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GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
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@ -123,8 +123,8 @@ GEN_VXFORM(vslo, 6, 16),
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GEN_VXFORM(vsro, 6, 17),
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GEN_VXFORM(vaddcuw, 0, 6),
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GEN_VXFORM(vsubcuw, 0, 22),
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GEN_VXFORM(vaddubs, 0, 8),
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GEN_VXFORM(vadduhs, 0, 9),
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GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM(vadduws, 0, 10),
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GEN_VXFORM(vaddsbs, 0, 12),
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GEN_VXFORM(vaddshs, 0, 13),
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