target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
This is the only caller. Adjust some commentary to talk about SCTLR_B instead of the vanishing function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210419202257.161730-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -975,20 +975,17 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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gen_aa32_st_i32(s, val, a32, index, OPC); \
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gen_aa32_st_i32(s, val, a32, index, OPC); \
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}
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}
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static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
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{
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b) {
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tcg_gen_rotri_i64(val, val, 32);
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}
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}
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static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc)
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int index, MemOp opc)
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{
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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TCGv addr = gen_aa32_addr(s, a32, opc);
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tcg_gen_qemu_ld_i64(val, addr, index, opc);
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tcg_gen_qemu_ld_i64(val, addr, index, opc);
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gen_aa32_frob64(s, val);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b) {
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tcg_gen_rotri_i64(val, val, 32);
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}
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tcg_temp_free(addr);
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tcg_temp_free(addr);
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}
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}
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@ -4987,16 +4984,13 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
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TCGv_i32 tmp2 = tcg_temp_new_i32();
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TCGv_i32 tmp2 = tcg_temp_new_i32();
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TCGv_i64 t64 = tcg_temp_new_i64();
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TCGv_i64 t64 = tcg_temp_new_i64();
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/* For AArch32, architecturally the 32-bit word at the lowest
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/*
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* For AArch32, architecturally the 32-bit word at the lowest
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* address is always Rt and the one at addr+4 is Rt2, even if
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* address is always Rt and the one at addr+4 is Rt2, even if
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* the CPU is big-endian. That means we don't want to do a
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* the CPU is big-endian. That means we don't want to do a
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* gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if
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* gen_aa32_ld_i64(), which checks SCTLR_B as if for an
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* for an architecturally 64-bit access, but instead do a
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* architecturally 64-bit access, but instead do a 64-bit access
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* 64-bit access using MO_BE if appropriate and then split
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* using MO_BE if appropriate and then split the two halves.
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* the two halves.
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* This only makes a difference for BE32 user-mode, where
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* frob64() must not flip the two halves of the 64-bit data
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* but this code must treat BE32 user-mode like BE32 system.
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*/
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*/
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TCGv taddr = gen_aa32_addr(s, addr, opc);
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TCGv taddr = gen_aa32_addr(s, addr, opc);
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@ -5056,14 +5050,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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TCGv_i64 n64 = tcg_temp_new_i64();
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TCGv_i64 n64 = tcg_temp_new_i64();
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t2 = load_reg(s, rt2);
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t2 = load_reg(s, rt2);
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/* For AArch32, architecturally the 32-bit word at the lowest
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/*
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* For AArch32, architecturally the 32-bit word at the lowest
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* address is always Rt and the one at addr+4 is Rt2, even if
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* address is always Rt and the one at addr+4 is Rt2, even if
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* the CPU is big-endian. Since we're going to treat this as a
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* the CPU is big-endian. Since we're going to treat this as a
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* single 64-bit BE store, we need to put the two halves in the
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* single 64-bit BE store, we need to put the two halves in the
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* opposite order for BE to LE, so that they end up in the right
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* opposite order for BE to LE, so that they end up in the right
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* places.
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* places. We don't want gen_aa32_st_i64, because that checks
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* We don't want gen_aa32_frob64() because that does the wrong
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* SCTLR_B as if for an architectural 64-bit access.
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* thing for BE32 usermode.
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*/
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*/
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if (s->be_data == MO_BE) {
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if (s->be_data == MO_BE) {
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tcg_gen_concat_i32_i64(n64, t2, t1);
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tcg_gen_concat_i32_i64(n64, t2, t1);
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