hw/arm_gic: Move NCPU definition to arm_gic.c
Move the NCPU definition to arm_gic.c: the maximum number of CPU interfaces is defined by the GIC architecture specification to be 8, so we don't need to have this #define in each of the sources files which currently includes arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
This commit is contained in:
parent
5181b50fc8
commit
386e29554e
|
@ -21,10 +21,8 @@
|
||||||
#include "sysbus.h"
|
#include "sysbus.h"
|
||||||
|
|
||||||
/* Configuration for arm_gic.c:
|
/* Configuration for arm_gic.c:
|
||||||
* max number of CPUs, how to ID current CPU
|
* how to ID current CPU
|
||||||
*/
|
*/
|
||||||
#define NCPU 4
|
|
||||||
|
|
||||||
static inline int gic_get_current_cpu(void)
|
static inline int gic_get_current_cpu(void)
|
||||||
{
|
{
|
||||||
return cpu_single_env->cpu_index;
|
return cpu_single_env->cpu_index;
|
||||||
|
@ -45,10 +43,6 @@ static int a15mp_priv_init(SysBusDevice *dev)
|
||||||
{
|
{
|
||||||
A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev);
|
A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev);
|
||||||
|
|
||||||
if (s->num_cpu > NCPU) {
|
|
||||||
hw_error("a15mp_priv_init: num-cpu may not be more than %d\n", NCPU);
|
|
||||||
}
|
|
||||||
|
|
||||||
gic_init(&s->gic, s->num_cpu, s->num_irq);
|
gic_init(&s->gic, s->num_cpu, s->num_irq);
|
||||||
|
|
||||||
/* Memory map (addresses are offsets from PERIPHBASE):
|
/* Memory map (addresses are offsets from PERIPHBASE):
|
||||||
|
|
|
@ -11,10 +11,8 @@
|
||||||
#include "sysbus.h"
|
#include "sysbus.h"
|
||||||
|
|
||||||
/* Configuration for arm_gic.c:
|
/* Configuration for arm_gic.c:
|
||||||
* max number of CPUs, how to ID current CPU
|
* how to ID current CPU
|
||||||
*/
|
*/
|
||||||
#define NCPU 4
|
|
||||||
|
|
||||||
static inline int
|
static inline int
|
||||||
gic_get_current_cpu(void)
|
gic_get_current_cpu(void)
|
||||||
{
|
{
|
||||||
|
@ -149,10 +147,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
|
||||||
SysBusDevice *busdev;
|
SysBusDevice *busdev;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (s->num_cpu > NCPU) {
|
|
||||||
hw_error("a9mp_priv_init: num-cpu may not be more than %d\n", NCPU);
|
|
||||||
}
|
|
||||||
|
|
||||||
gic_init(&s->gic, s->num_cpu, s->num_irq);
|
gic_init(&s->gic, s->num_cpu, s->num_irq);
|
||||||
|
|
||||||
s->mptimer = qdev_create(NULL, "arm_mptimer");
|
s->mptimer = qdev_create(NULL, "arm_mptimer");
|
||||||
|
|
|
@ -10,8 +10,6 @@
|
||||||
#include "sysbus.h"
|
#include "sysbus.h"
|
||||||
#include "qemu-timer.h"
|
#include "qemu-timer.h"
|
||||||
|
|
||||||
#define NCPU 4
|
|
||||||
|
|
||||||
static inline int
|
static inline int
|
||||||
gic_get_current_cpu(void)
|
gic_get_current_cpu(void)
|
||||||
{
|
{
|
||||||
|
|
13
hw/arm_gic.c
13
hw/arm_gic.c
|
@ -15,6 +15,13 @@
|
||||||
#define GIC_MAXIRQ 1020
|
#define GIC_MAXIRQ 1020
|
||||||
/* First 32 are private to each CPU (SGIs and PPIs). */
|
/* First 32 are private to each CPU (SGIs and PPIs). */
|
||||||
#define GIC_INTERNAL 32
|
#define GIC_INTERNAL 32
|
||||||
|
/* Maximum number of possible CPU interfaces, determined by GIC architecture */
|
||||||
|
#ifdef NVIC
|
||||||
|
#define NCPU 1
|
||||||
|
#else
|
||||||
|
#define NCPU 8
|
||||||
|
#endif
|
||||||
|
|
||||||
//#define DEBUG_GIC
|
//#define DEBUG_GIC
|
||||||
|
|
||||||
#ifdef DEBUG_GIC
|
#ifdef DEBUG_GIC
|
||||||
|
@ -50,7 +57,7 @@ typedef struct gic_irq_state
|
||||||
unsigned trigger:1; /* nonzero = edge triggered. */
|
unsigned trigger:1; /* nonzero = edge triggered. */
|
||||||
} gic_irq_state;
|
} gic_irq_state;
|
||||||
|
|
||||||
#define ALL_CPU_MASK ((1 << NCPU) - 1)
|
#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
|
||||||
#if NCPU > 1
|
#if NCPU > 1
|
||||||
#define NUM_CPU(s) ((s)->num_cpu)
|
#define NUM_CPU(s) ((s)->num_cpu)
|
||||||
#else
|
#else
|
||||||
|
@ -813,6 +820,10 @@ static void gic_init(gic_state *s, int num_irq)
|
||||||
|
|
||||||
#if NCPU > 1
|
#if NCPU > 1
|
||||||
s->num_cpu = num_cpu;
|
s->num_cpu = num_cpu;
|
||||||
|
if (s->num_cpu > NCPU) {
|
||||||
|
hw_error("requested %u CPUs exceeds GIC maximum %d\n",
|
||||||
|
num_cpu, NCPU);
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
s->num_irq = num_irq + GIC_BASE_IRQ;
|
s->num_irq = num_irq + GIC_BASE_IRQ;
|
||||||
if (s->num_irq > GIC_MAXIRQ) {
|
if (s->num_irq > GIC_MAXIRQ) {
|
||||||
|
|
|
@ -15,7 +15,6 @@
|
||||||
#include "arm-misc.h"
|
#include "arm-misc.h"
|
||||||
#include "exec-memory.h"
|
#include "exec-memory.h"
|
||||||
|
|
||||||
#define NCPU 1
|
|
||||||
#define NVIC 1
|
#define NVIC 1
|
||||||
|
|
||||||
/* Only a single "CPU" interface is present. */
|
/* Only a single "CPU" interface is present. */
|
||||||
|
|
|
@ -174,7 +174,6 @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
#define EXYNOS4210_GIC_NIRQ 160
|
#define EXYNOS4210_GIC_NIRQ 160
|
||||||
#define NCPU EXYNOS4210_NCPUS
|
|
||||||
|
|
||||||
#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
|
#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
|
||||||
#define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000
|
#define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000
|
||||||
|
@ -275,8 +274,8 @@ typedef struct {
|
||||||
gic_state gic;
|
gic_state gic;
|
||||||
MemoryRegion cpu_container;
|
MemoryRegion cpu_container;
|
||||||
MemoryRegion dist_container;
|
MemoryRegion dist_container;
|
||||||
MemoryRegion cpu_alias[NCPU];
|
MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
|
||||||
MemoryRegion dist_alias[NCPU];
|
MemoryRegion dist_alias[EXYNOS4210_NCPUS];
|
||||||
uint32_t num_cpu;
|
uint32_t num_cpu;
|
||||||
} Exynos4210GicState;
|
} Exynos4210GicState;
|
||||||
|
|
||||||
|
@ -359,7 +358,7 @@ type_init(exynos4210_gic_register_types)
|
||||||
typedef struct {
|
typedef struct {
|
||||||
SysBusDevice busdev;
|
SysBusDevice busdev;
|
||||||
|
|
||||||
qemu_irq pic_irq[NCPU]; /* output IRQs to PICs */
|
qemu_irq pic_irq[EXYNOS4210_NCPUS]; /* output IRQs to PICs */
|
||||||
uint32_t gpio_level[EXYNOS4210_IRQ_GATE_NINPUTS]; /* Input levels */
|
uint32_t gpio_level[EXYNOS4210_IRQ_GATE_NINPUTS]; /* Input levels */
|
||||||
} Exynos4210IRQGateState;
|
} Exynos4210IRQGateState;
|
||||||
|
|
||||||
|
@ -424,7 +423,7 @@ static int exynos4210_irq_gate_init(SysBusDevice *dev)
|
||||||
EXYNOS4210_IRQ_GATE_NINPUTS);
|
EXYNOS4210_IRQ_GATE_NINPUTS);
|
||||||
|
|
||||||
/* Connect SysBusDev irqs to device specific irqs */
|
/* Connect SysBusDev irqs to device specific irqs */
|
||||||
for (i = 0; i < NCPU; i++) {
|
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
|
||||||
sysbus_init_irq(dev, &s->pic_irq[i]);
|
sysbus_init_irq(dev, &s->pic_irq[i]);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -9,8 +9,6 @@
|
||||||
|
|
||||||
#include "sysbus.h"
|
#include "sysbus.h"
|
||||||
|
|
||||||
#define NCPU 1
|
|
||||||
|
|
||||||
/* Only a single "CPU" interface is present. */
|
/* Only a single "CPU" interface is present. */
|
||||||
static inline int
|
static inline int
|
||||||
gic_get_current_cpu(void)
|
gic_get_current_cpu(void)
|
||||||
|
@ -40,7 +38,7 @@ static int realview_gic_init(SysBusDevice *dev)
|
||||||
* number of interrupt lines, so we don't need to expose this as
|
* number of interrupt lines, so we don't need to expose this as
|
||||||
* a qdev property.
|
* a qdev property.
|
||||||
*/
|
*/
|
||||||
gic_init(&s->gic, 96);
|
gic_init(&s->gic, 1, 96);
|
||||||
realview_gic_map_setup(s);
|
realview_gic_map_setup(s);
|
||||||
sysbus_init_mmio(dev, &s->container);
|
sysbus_init_mmio(dev, &s->container);
|
||||||
return 0;
|
return 0;
|
||||||
|
|
Loading…
Reference in a new issue