hw/ppc/pnv_homer: add PowerNV homer device model
add PnvHomer device model to emulate homer memory access for pstate table, occ-sensors, slw, occ static and dynamic values for Power8 and Power9 chips. Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> Message-Id: <20190912093056.4516-4-bala24@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Balamuruhan S
David Gibson
parent
f3db82660d
commit
3887d24123
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@ -9,6 +9,7 @@ obj-$(CONFIG_PSERIES) += spapr_tpm_proxy.o
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obj-$(CONFIG_SPAPR_RNG) += spapr_rng.o
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# IBM PowerNV
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obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o
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obj-$(CONFIG_POWERNV) += pnv_homer.o
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ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
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obj-y += spapr_pci_vfio.o spapr_pci_nvlink2.o
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endif
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30
hw/ppc/pnv.c
30
hw/ppc/pnv.c
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@ -860,6 +860,11 @@ static void pnv_chip_power8_instance_init(Object *obj)
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TYPE_PNV8_OCC, &error_abort, NULL);
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object_property_add_const_link(OBJECT(&chip8->occ), "psi",
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OBJECT(&chip8->psi), &error_abort);
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object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
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TYPE_PNV8_HOMER, &error_abort, NULL);
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object_property_add_const_link(OBJECT(&chip8->homer), "chip", obj,
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&error_abort);
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}
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static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
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@ -957,6 +962,16 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
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/* OCC SRAM model */
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memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip),
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&chip8->occ.sram_regs);
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/* HOMER */
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object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
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&local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
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&chip8->homer.regs);
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}
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static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
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@ -1039,6 +1054,11 @@ static void pnv_chip_power9_instance_init(Object *obj)
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TYPE_PNV9_OCC, &error_abort, NULL);
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object_property_add_const_link(OBJECT(&chip9->occ), "psi",
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OBJECT(&chip9->psi), &error_abort);
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object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
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TYPE_PNV9_HOMER, &error_abort, NULL);
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object_property_add_const_link(OBJECT(&chip9->homer), "chip", obj,
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&error_abort);
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}
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static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
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@ -1149,6 +1169,16 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
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/* OCC SRAM model */
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memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip),
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&chip9->occ.sram_regs);
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/* HOMER */
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object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
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&local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
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&chip9->homer.regs);
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}
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static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
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272
hw/ppc/pnv_homer.c
Normal file
272
hw/ppc/pnv_homer.c
Normal file
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@ -0,0 +1,272 @@
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/*
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* QEMU PowerPC PowerNV Emulation of a few HOMER related registers
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*
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* Copyright (c) 2019, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "exec/hwaddr.h"
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#include "exec/memory.h"
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#include "sysemu/cpus.h"
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#include "hw/qdev-core.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_homer.h"
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static bool core_max_array(PnvHomer *homer, hwaddr addr)
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{
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int i;
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PnvHomerClass *hmrc = PNV_HOMER_GET_CLASS(homer);
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for (i = 0; i <= homer->chip->nr_cores; i++) {
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if (addr == (hmrc->core_max_base + i)) {
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return true;
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}
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}
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return false;
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}
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/* P8 Pstate table */
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#define PNV8_OCC_PSTATE_VERSION 0x1f8001
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#define PNV8_OCC_PSTATE_MIN 0x1f8003
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#define PNV8_OCC_PSTATE_VALID 0x1f8000
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#define PNV8_OCC_PSTATE_THROTTLE 0x1f8002
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#define PNV8_OCC_PSTATE_NOM 0x1f8004
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#define PNV8_OCC_PSTATE_TURBO 0x1f8005
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#define PNV8_OCC_PSTATE_ULTRA_TURBO 0x1f8006
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#define PNV8_OCC_PSTATE_DATA 0x1f8008
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#define PNV8_OCC_PSTATE_ID_ZERO 0x1f8010
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#define PNV8_OCC_PSTATE_ID_ONE 0x1f8018
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#define PNV8_OCC_PSTATE_ID_TWO 0x1f8020
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#define PNV8_OCC_VDD_VOLTAGE_IDENTIFIER 0x1f8012
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#define PNV8_OCC_VCS_VOLTAGE_IDENTIFIER 0x1f8013
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#define PNV8_OCC_PSTATE_ZERO_FREQUENCY 0x1f8014
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#define PNV8_OCC_PSTATE_ONE_FREQUENCY 0x1f801c
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#define PNV8_OCC_PSTATE_TWO_FREQUENCY 0x1f8024
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#define PNV8_CORE_MAX_BASE 0x1f8810
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static uint64_t pnv_power8_homer_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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switch (addr) {
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case PNV8_OCC_PSTATE_VERSION:
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case PNV8_OCC_PSTATE_MIN:
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case PNV8_OCC_PSTATE_ID_ZERO:
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return 0;
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case PNV8_OCC_PSTATE_VALID:
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case PNV8_OCC_PSTATE_THROTTLE:
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case PNV8_OCC_PSTATE_NOM:
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case PNV8_OCC_PSTATE_TURBO:
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case PNV8_OCC_PSTATE_ID_ONE:
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case PNV8_OCC_VDD_VOLTAGE_IDENTIFIER:
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case PNV8_OCC_VCS_VOLTAGE_IDENTIFIER:
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return 1;
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case PNV8_OCC_PSTATE_ULTRA_TURBO:
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case PNV8_OCC_PSTATE_ID_TWO:
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return 2;
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case PNV8_OCC_PSTATE_DATA:
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return 0x1000000000000000;
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/* P8 frequency for 0, 1, and 2 pstates */
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case PNV8_OCC_PSTATE_ZERO_FREQUENCY:
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case PNV8_OCC_PSTATE_ONE_FREQUENCY:
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case PNV8_OCC_PSTATE_TWO_FREQUENCY:
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return 3000;
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}
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/* pstate table core max array */
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if (core_max_array(homer, addr)) {
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return 1;
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}
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return 0;
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}
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static void pnv_power8_homer_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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/* callback function defined to homer write */
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return;
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}
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static const MemoryRegionOps pnv_power8_homer_ops = {
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.read = pnv_power8_homer_read,
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.write = pnv_power8_homer_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.impl.min_access_size = 1,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_homer_power8_class_init(ObjectClass *klass, void *data)
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{
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PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
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homer->homer_size = PNV_HOMER_SIZE;
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homer->homer_ops = &pnv_power8_homer_ops;
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homer->core_max_base = PNV8_CORE_MAX_BASE;
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}
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static const TypeInfo pnv_homer_power8_type_info = {
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.name = TYPE_PNV8_HOMER,
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.parent = TYPE_PNV_HOMER,
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.instance_size = sizeof(PnvHomer),
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.class_init = pnv_homer_power8_class_init,
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};
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/* P9 Pstate table */
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#define PNV9_OCC_PSTATE_ID_ZERO 0xe2018
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#define PNV9_OCC_PSTATE_ID_ONE 0xe2020
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#define PNV9_OCC_PSTATE_ID_TWO 0xe2028
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#define PNV9_OCC_PSTATE_DATA 0xe2000
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#define PNV9_OCC_PSTATE_DATA_AREA 0xe2008
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#define PNV9_OCC_PSTATE_MIN 0xe2003
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#define PNV9_OCC_PSTATE_NOM 0xe2004
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#define PNV9_OCC_PSTATE_TURBO 0xe2005
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#define PNV9_OCC_PSTATE_ULTRA_TURBO 0xe2818
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#define PNV9_OCC_MAX_PSTATE_ULTRA_TURBO 0xe2006
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#define PNV9_OCC_PSTATE_MAJOR_VERSION 0xe2001
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#define PNV9_OCC_OPAL_RUNTIME_DATA 0xe2b85
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#define PNV9_CHIP_HOMER_IMAGE_POINTER 0x200008
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#define PNV9_CHIP_HOMER_BASE 0x0
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#define PNV9_OCC_PSTATE_ZERO_FREQUENCY 0xe201c
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#define PNV9_OCC_PSTATE_ONE_FREQUENCY 0xe2024
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#define PNV9_OCC_PSTATE_TWO_FREQUENCY 0xe202c
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#define PNV9_OCC_ROLE_MASTER_OR_SLAVE 0xe2002
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#define PNV9_CORE_MAX_BASE 0xe2819
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static uint64_t pnv_power9_homer_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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switch (addr) {
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case PNV9_OCC_MAX_PSTATE_ULTRA_TURBO:
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case PNV9_OCC_PSTATE_ID_ZERO:
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return 0;
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case PNV9_OCC_PSTATE_DATA:
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case PNV9_OCC_ROLE_MASTER_OR_SLAVE:
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case PNV9_OCC_PSTATE_NOM:
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case PNV9_OCC_PSTATE_TURBO:
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case PNV9_OCC_PSTATE_ID_ONE:
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case PNV9_OCC_PSTATE_ULTRA_TURBO:
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case PNV9_OCC_OPAL_RUNTIME_DATA:
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return 1;
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case PNV9_OCC_PSTATE_MIN:
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case PNV9_OCC_PSTATE_ID_TWO:
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return 2;
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/* 3000 khz frequency for 0, 1, and 2 pstates */
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case PNV9_OCC_PSTATE_ZERO_FREQUENCY:
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case PNV9_OCC_PSTATE_ONE_FREQUENCY:
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case PNV9_OCC_PSTATE_TWO_FREQUENCY:
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return 3000;
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case PNV9_OCC_PSTATE_MAJOR_VERSION:
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return 0x90;
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case PNV9_CHIP_HOMER_BASE:
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case PNV9_OCC_PSTATE_DATA_AREA:
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case PNV9_CHIP_HOMER_IMAGE_POINTER:
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return 0x1000000000000000;
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}
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/* pstate table core max array */
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if (core_max_array(homer, addr)) {
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return 1;
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}
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return 0;
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}
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static void pnv_power9_homer_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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/* callback function defined to homer write */
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return;
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}
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static const MemoryRegionOps pnv_power9_homer_ops = {
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.read = pnv_power9_homer_read,
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.write = pnv_power9_homer_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.impl.min_access_size = 1,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_homer_power9_class_init(ObjectClass *klass, void *data)
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{
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PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
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homer->homer_size = PNV9_HOMER_SIZE;
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homer->homer_ops = &pnv_power9_homer_ops;
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homer->core_max_base = PNV9_CORE_MAX_BASE;
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}
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static const TypeInfo pnv_homer_power9_type_info = {
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.name = TYPE_PNV9_HOMER,
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.parent = TYPE_PNV_HOMER,
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.instance_size = sizeof(PnvHomer),
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.class_init = pnv_homer_power9_class_init,
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};
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static void pnv_homer_realize(DeviceState *dev, Error **errp)
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{
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PnvHomer *homer = PNV_HOMER(dev);
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PnvHomerClass *hmrc = PNV_HOMER_GET_CLASS(homer);
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Object *obj;
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Error *local_err = NULL;
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obj = object_property_get_link(OBJECT(dev), "chip", &local_err);
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if (!obj) {
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error_propagate(errp, local_err);
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error_prepend(errp, "required link 'chip' not found: ");
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return;
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}
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homer->chip = PNV_CHIP(obj);
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/* homer region */
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memory_region_init_io(&homer->regs, OBJECT(dev),
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hmrc->homer_ops, homer, "homer-main-memory",
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hmrc->homer_size);
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}
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static void pnv_homer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = pnv_homer_realize;
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dc->desc = "PowerNV HOMER Memory";
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}
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static const TypeInfo pnv_homer_type_info = {
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.name = TYPE_PNV_HOMER,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvHomer),
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.class_init = pnv_homer_class_init,
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.class_size = sizeof(PnvHomerClass),
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.abstract = true,
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};
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static void pnv_homer_register_types(void)
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{
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type_register_static(&pnv_homer_type_info);
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type_register_static(&pnv_homer_power8_type_info);
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type_register_static(&pnv_homer_power9_type_info);
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}
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type_init(pnv_homer_register_types);
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@ -26,6 +26,7 @@
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#include "hw/ppc/pnv_lpc.h"
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#include "hw/ppc/pnv_psi.h"
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#include "hw/ppc/pnv_occ.h"
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#include "hw/ppc/pnv_homer.h"
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#include "hw/ppc/pnv_xive.h"
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#include "hw/ppc/pnv_core.h"
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@ -76,6 +77,7 @@ typedef struct Pnv8Chip {
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PnvLpcController lpc;
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Pnv8Psi psi;
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PnvOCC occ;
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PnvHomer homer;
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} Pnv8Chip;
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#define TYPE_PNV9_CHIP "pnv9-chip"
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@ -90,6 +92,7 @@ typedef struct Pnv9Chip {
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Pnv9Psi psi;
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PnvLpcController lpc;
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PnvOCC occ;
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PnvHomer homer;
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uint32_t nr_quads;
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PnvQuad *quads;
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53
include/hw/ppc/pnv_homer.h
Normal file
53
include/hw/ppc/pnv_homer.h
Normal file
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@ -0,0 +1,53 @@
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/*
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* QEMU PowerPC PowerNV Emulation of a few HOMER related registers
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*
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* Copyright (c) 2019, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU Lesser General Public
|
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* License as published by the Free Software Foundation; either
|
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* version 2 of the License, or (at your option) any later version.
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*
|
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* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
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* Lesser General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU Lesser General Public
|
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_HOMER_H
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#define PPC_PNV_HOMER_H
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#include "hw/ppc/pnv.h"
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#define TYPE_PNV_HOMER "pnv-homer"
|
||||
#define PNV_HOMER(obj) OBJECT_CHECK(PnvHomer, (obj), TYPE_PNV_HOMER)
|
||||
#define TYPE_PNV8_HOMER TYPE_PNV_HOMER "-POWER8"
|
||||
#define PNV8_HOMER(obj) OBJECT_CHECK(PnvHomer, (obj), TYPE_PNV8_HOMER)
|
||||
#define TYPE_PNV9_HOMER TYPE_PNV_HOMER "-POWER9"
|
||||
#define PNV9_HOMER(obj) OBJECT_CHECK(PnvHomer, (obj), TYPE_PNV9_HOMER)
|
||||
|
||||
typedef struct PnvHomer {
|
||||
DeviceState parent;
|
||||
|
||||
struct PnvChip *chip;
|
||||
MemoryRegion regs;
|
||||
} PnvHomer;
|
||||
|
||||
#define PNV_HOMER_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(PnvHomerClass, (klass), TYPE_PNV_HOMER)
|
||||
#define PNV_HOMER_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(PnvHomerClass, (obj), TYPE_PNV_HOMER)
|
||||
|
||||
typedef struct PnvHomerClass {
|
||||
DeviceClass parent_class;
|
||||
|
||||
int homer_size;
|
||||
const MemoryRegionOps *homer_ops;
|
||||
|
||||
hwaddr core_max_base;
|
||||
} PnvHomerClass;
|
||||
|
||||
#endif /* PPC_PNV_HOMER_H */
|
||||
Loading…
Reference in a new issue