Fix BD flag handling, cause register contents, implement some more bits
for R2 interrupt handling. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
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36f696517b
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39d51eb8bc
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@ -20,20 +20,15 @@ void cpu_mips_update_irq(CPUState *env)
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void cpu_mips_irq_request(void *opaque, int irq, int level)
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void cpu_mips_irq_request(void *opaque, int irq, int level)
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{
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{
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CPUState *env = first_cpu;
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CPUState *env = (CPUState *)opaque;
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uint32_t mask;
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if (irq < 0 || irq > 7)
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if (irq >= 16)
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return;
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return;
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mask = 1 << (irq + CP0Ca_IP);
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if (level) {
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if (level) {
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env->CP0_Cause |= mask;
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env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
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} else {
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} else {
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env->CP0_Cause &= ~mask;
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env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
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}
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}
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cpu_mips_update_irq(env);
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cpu_mips_update_irq(env);
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}
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}
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@ -28,6 +28,9 @@ static void cpu_mips_update_count (CPUState *env, uint32_t count,
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uint64_t now, next;
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uint64_t now, next;
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uint32_t tmp;
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uint32_t tmp;
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if (env->CP0_Cause & (1 << CP0Ca_DC))
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return;
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tmp = count;
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tmp = count;
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if (count == compare)
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if (count == compare)
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tmp++;
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tmp++;
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@ -57,6 +60,8 @@ void cpu_mips_store_count (CPUState *env, uint32_t value)
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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{
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{
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cpu_mips_update_count(env, cpu_mips_get_count(env), value);
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cpu_mips_update_count(env, cpu_mips_get_count(env), value);
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if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
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env->CP0_Cause &= ~(1 << CP0Ca_TI);
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cpu_mips_irq_request(env, 7, 0);
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cpu_mips_irq_request(env, 7, 0);
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}
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}
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@ -71,6 +76,8 @@ static void mips_timer_cb (void *opaque)
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}
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}
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#endif
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#endif
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cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
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cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
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if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
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env->CP0_Cause |= 1 << CP0Ca_TI;
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cpu_mips_irq_request(env, 7, 1);
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cpu_mips_irq_request(env, 7, 1);
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}
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}
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@ -295,9 +295,12 @@ void do_interrupt (CPUState *env)
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/* If the exception was raised from a delay slot,
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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come back to the jump. */
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env->CP0_DEPC = env->PC - 4;
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env->CP0_DEPC = env->PC - 4;
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if (!(env->hflags & MIPS_HFLAG_EXL))
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env->CP0_Cause |= (1 << CP0Ca_BD);
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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} else {
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env->CP0_DEPC = env->PC;
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env->CP0_DEPC = env->PC;
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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}
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}
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enter_debug_mode:
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enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM;
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env->hflags |= MIPS_HFLAG_DM;
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@ -318,9 +321,12 @@ void do_interrupt (CPUState *env)
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/* If the exception was raised from a delay slot,
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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come back to the jump. */
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env->CP0_ErrorEPC = env->PC - 4;
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env->CP0_ErrorEPC = env->PC - 4;
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if (!(env->hflags & MIPS_HFLAG_EXL))
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env->CP0_Cause |= (1 << CP0Ca_BD);
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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} else {
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env->CP0_ErrorEPC = env->PC;
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env->CP0_ErrorEPC = env->PC;
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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}
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}
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env->hflags |= MIPS_HFLAG_ERL;
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env->hflags |= MIPS_HFLAG_ERL;
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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@ -364,7 +370,8 @@ void do_interrupt (CPUState *env)
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goto set_EPC;
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goto set_EPC;
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case EXCP_CpU:
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case EXCP_CpU:
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cause = 11;
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cause = 11;
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env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
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env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
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(env->error_code << CP0Ca_CE);
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goto set_EPC;
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goto set_EPC;
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case EXCP_OVERFLOW:
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case EXCP_OVERFLOW:
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cause = 12;
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cause = 12;
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@ -385,11 +392,12 @@ void do_interrupt (CPUState *env)
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/* If the exception was raised from a delay slot,
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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come back to the jump. */
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env->CP0_EPC = env->PC - 4;
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env->CP0_EPC = env->PC - 4;
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env->CP0_Cause |= 0x80000000;
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if (!(env->hflags & MIPS_HFLAG_EXL))
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env->CP0_Cause |= (1 << CP0Ca_BD);
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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} else {
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env->CP0_EPC = env->PC;
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env->CP0_EPC = env->PC;
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env->CP0_Cause &= ~0x80000000;
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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}
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}
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if (env->CP0_Status & (1 << CP0St_BEV)) {
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if (env->CP0_Status & (1 << CP0St_BEV)) {
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env->PC = (int32_t)0xBFC00200;
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env->PC = (int32_t)0xBFC00200;
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@ -1397,7 +1397,12 @@ void op_mtc0_srsmap (void)
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void op_mtc0_cause (void)
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void op_mtc0_cause (void)
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{
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{
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env->CP0_Cause = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);
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uint32_t mask = 0x00C00300;
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if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
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mask |= 1 << CP0Ca_DC;
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env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);
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/* Handle the software interrupt as an hardware one, as they
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/* Handle the software interrupt as an hardware one, as they
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are very similar */
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are very similar */
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