target/arm: Implement SVE Bitwise Logical - Unpredicated Group
These were the instructions that were stubbed out when introducing the decode skeleton. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -42,22 +42,61 @@
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* Implement all of the translator functions referenced by the decoder.
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*/
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static bool trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn)
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/* Invoke a vector expander on two Zregs. */
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static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
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int esz, int rd, int rn)
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{
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return false;
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if (sve_access_check(s)) {
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unsigned vsz = vec_full_reg_size(s);
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gvec_fn(esz, vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rn), vsz, vsz);
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}
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return true;
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}
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static bool trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn)
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/* Invoke a vector expander on three Zregs. */
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static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
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int esz, int rd, int rn, int rm)
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{
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return false;
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if (sve_access_check(s)) {
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unsigned vsz = vec_full_reg_size(s);
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gvec_fn(esz, vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rn),
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vec_full_reg_offset(s, rm), vsz, vsz);
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}
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return true;
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}
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static bool trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn)
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/* Invoke a vector move on two Zregs. */
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static bool do_mov_z(DisasContext *s, int rd, int rn)
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{
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return false;
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return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
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}
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static bool trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn)
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/*
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*** SVE Logical - Unpredicated Group
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*/
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static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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return false;
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return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
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}
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static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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if (a->rn == a->rm) { /* MOV */
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return do_mov_z(s, a->rd, a->rn);
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} else {
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return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
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}
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}
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static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
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}
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static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
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}
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