target/arm: Use tcg_gen_gvec_bitsel
This replaces 3 target-specific implementations for BIT, BIF, and BSL. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190518191934.21887-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -704,6 +704,15 @@ static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm,
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vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s));
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}
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/* Expand a 4-operand AdvSIMD vector operation using an expander function. */
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static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
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int rx, GVecGen4Fn *gvec_fn, int vece)
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{
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gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
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vec_full_reg_offset(s, rm), vec_full_reg_offset(s, rx),
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is_q ? 16 : 8, vec_full_reg_size(s));
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}
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/* Expand a 2-operand + immediate AdvSIMD vector operation using
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* an op descriptor.
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*/
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@ -10918,13 +10927,13 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
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return;
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case 5: /* BSL bitwise select */
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gen_gvec_op3(s, is_q, rd, rn, rm, &bsl_op);
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gen_gvec_fn4(s, is_q, rd, rd, rn, rm, tcg_gen_gvec_bitsel, 0);
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return;
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case 6: /* BIT, bitwise insert if true */
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gen_gvec_op3(s, is_q, rd, rn, rm, &bit_op);
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gen_gvec_fn4(s, is_q, rd, rm, rn, rd, tcg_gen_gvec_bitsel, 0);
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return;
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case 7: /* BIF, bitwise insert if false */
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gen_gvec_op3(s, is_q, rd, rn, rm, &bif_op);
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gen_gvec_fn4(s, is_q, rd, rm, rd, rn, tcg_gen_gvec_bitsel, 0);
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return;
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default:
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@ -122,5 +122,7 @@ typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
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uint32_t, uint32_t);
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typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
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uint32_t, uint32_t, uint32_t);
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typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
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uint32_t, uint32_t, uint32_t);
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#endif /* TARGET_ARM_TRANSLATE_A64_H */
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@ -5755,72 +5755,6 @@ static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
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return 1;
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}
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/*
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* Expanders for VBitOps_VBIF, VBIT, VBSL.
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*/
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static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rm);
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tcg_gen_and_i64(rn, rn, rd);
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tcg_gen_xor_i64(rd, rm, rn);
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}
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static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rd);
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tcg_gen_and_i64(rn, rn, rm);
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tcg_gen_xor_i64(rd, rd, rn);
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}
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static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rd);
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tcg_gen_andc_i64(rn, rn, rm);
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tcg_gen_xor_i64(rd, rd, rn);
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}
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static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rm);
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tcg_gen_and_vec(vece, rn, rn, rd);
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tcg_gen_xor_vec(vece, rd, rm, rn);
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}
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static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rd);
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tcg_gen_and_vec(vece, rn, rn, rm);
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tcg_gen_xor_vec(vece, rd, rd, rn);
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}
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static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rd);
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tcg_gen_andc_vec(vece, rn, rn, rm);
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tcg_gen_xor_vec(vece, rd, rd, rn);
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}
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const GVecGen3 bsl_op = {
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.fni8 = gen_bsl_i64,
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.fniv = gen_bsl_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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const GVecGen3 bit_op = {
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.fni8 = gen_bit_i64,
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.fniv = gen_bit_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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const GVecGen3 bif_op = {
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.fni8 = gen_bif_i64,
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.fniv = gen_bif_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
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{
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tcg_gen_vec_sar8i_i64(a, a, shift);
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@ -6570,16 +6504,16 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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vec_size, vec_size);
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break;
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case 5: /* VBSL */
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tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size, &bsl_op);
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tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size);
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break;
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case 6: /* VBIT */
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tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size, &bit_op);
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tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,
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vec_size, vec_size);
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break;
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case 7: /* VBIF */
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tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size, &bif_op);
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tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,
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vec_size, vec_size);
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break;
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}
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return 0;
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@ -238,9 +238,6 @@ static inline void gen_ss_advance(DisasContext *s)
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}
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/* Vector operations shared between ARM and AArch64. */
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extern const GVecGen3 bsl_op;
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extern const GVecGen3 bit_op;
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extern const GVecGen3 bif_op;
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extern const GVecGen3 mla_op[4];
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extern const GVecGen3 mls_op[4];
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extern const GVecGen3 cmtst_op[4];
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