nvic: set pending status for not active interrupts
According to ARM DUI 0552A 4.2.10. NVIC set pending status also for disabled interrupts. Correct the logic for when interrupts are marked pending both on input level transition and when interrupts are dismissed, to match the NVIC behaviour rather than the 11MPCore GIC. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -156,6 +156,17 @@ static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
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}
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}
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}
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}
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static void gic_set_irq_nvic(GICState *s, int irq, int level,
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int cm, int target)
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{
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if (level) {
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GIC_SET_LEVEL(irq, cm);
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GIC_SET_PENDING(irq, target);
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} else {
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GIC_CLEAR_LEVEL(irq, cm);
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}
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}
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static void gic_set_irq_generic(GICState *s, int irq, int level,
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static void gic_set_irq_generic(GICState *s, int irq, int level,
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int cm, int target)
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int cm, int target)
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{
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{
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@ -201,8 +212,10 @@ static void gic_set_irq(void *opaque, int irq, int level)
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return;
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return;
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}
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}
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if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
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if (s->revision == REV_11MPCORE) {
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gic_set_irq_11mpcore(s, irq, level, cm, target);
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gic_set_irq_11mpcore(s, irq, level, cm, target);
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} else if (s->revision == REV_NVIC) {
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gic_set_irq_nvic(s, irq, level, cm, target);
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} else {
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} else {
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gic_set_irq_generic(s, irq, level, cm, target);
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gic_set_irq_generic(s, irq, level, cm, target);
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}
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}
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@ -568,7 +581,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
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return; /* No active IRQ. */
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return; /* No active IRQ. */
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}
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}
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if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
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if (s->revision == REV_11MPCORE) {
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/* Mark level triggered interrupts as pending if they are still
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/* Mark level triggered interrupts as pending if they are still
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raised. */
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raised. */
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if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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@ -576,6 +589,11 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
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DPRINTF("Set %d pending mask %x\n", irq, cm);
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DPRINTF("Set %d pending mask %x\n", irq, cm);
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GIC_SET_PENDING(irq, cm);
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GIC_SET_PENDING(irq, cm);
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}
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}
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} else if (s->revision == REV_NVIC) {
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if (GIC_TEST_LEVEL(irq, cm)) {
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DPRINTF("Set nvic %d pending mask %x\n", irq, cm);
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GIC_SET_PENDING(irq, cm);
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}
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}
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}
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group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
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group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
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