target/hppa: Convert to CPUClass::tlb_fill
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -163,9 +163,8 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
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cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
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cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
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cc->gdb_read_register = hppa_cpu_gdb_read_register;
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cc->gdb_read_register = hppa_cpu_gdb_read_register;
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cc->gdb_write_register = hppa_cpu_gdb_write_register;
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cc->gdb_write_register = hppa_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->tlb_fill = hppa_cpu_tlb_fill;
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cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault;
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#ifndef CONFIG_USER_ONLY
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#else
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cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
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cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
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dc->vmsd = &vmstate_hppa_cpu;
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dc->vmsd = &vmstate_hppa_cpu;
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#endif
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#endif
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@ -360,10 +360,10 @@ int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void hppa_cpu_do_interrupt(CPUState *cpu);
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void hppa_cpu_do_interrupt(CPUState *cpu);
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bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
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bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
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void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
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#ifdef CONFIG_USER_ONLY
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bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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int rw, int midx);
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bool probe, uintptr_t retaddr);
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#else
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#ifndef CONFIG_USER_ONLY
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int type, hwaddr *pphys, int *pprot);
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int type, hwaddr *pphys, int *pprot);
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extern const MemoryRegionOps hppa_io_eir_ops;
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extern const MemoryRegionOps hppa_io_eir_ops;
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@ -25,8 +25,9 @@
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#include "trace.h"
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#include "trace.h"
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#ifdef CONFIG_USER_ONLY
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#ifdef CONFIG_USER_ONLY
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int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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int size, int rw, int mmu_idx)
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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HPPACPU *cpu = HPPA_CPU(cs);
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@ -34,7 +35,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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which would affect si_code. */
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which would affect si_code. */
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cs->exception_index = EXCP_DMP;
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cs->exception_index = EXCP_DMP;
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cpu->env.cr[CR_IOR] = address;
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cpu->env.cr[CR_IOR] = address;
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return 1;
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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#else
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#else
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static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
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static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
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@ -213,8 +214,9 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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return excp == EXCP_DTLB_MISS ? -1 : phys;
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return excp == EXCP_DTLB_MISS ? -1 : phys;
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}
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}
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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MMUAccessType type, int mmu_idx, uintptr_t retaddr)
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MMUAccessType type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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HPPACPU *cpu = HPPA_CPU(cs);
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CPUHPPAState *env = &cpu->env;
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CPUHPPAState *env = &cpu->env;
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@ -236,6 +238,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
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excp = hppa_get_physical_address(env, addr, mmu_idx,
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excp = hppa_get_physical_address(env, addr, mmu_idx,
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a_prot, &phys, &prot);
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a_prot, &phys, &prot);
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if (unlikely(excp >= 0)) {
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if (unlikely(excp >= 0)) {
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if (probe) {
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return false;
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}
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trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx);
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trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx);
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/* Failure. Raise the indicated exception. */
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/* Failure. Raise the indicated exception. */
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cs->exception_index = excp;
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cs->exception_index = excp;
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@ -252,6 +257,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
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/* Success! Store the translation into the QEMU TLB. */
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/* Success! Store the translation into the QEMU TLB. */
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tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
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tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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prot, mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType type, int mmu_idx, uintptr_t retaddr)
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{
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hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr);
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}
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}
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/* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */
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/* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */
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