target/riscv: Set the virtualised MMU mode when doing hyp accesses
When performing the hypervisor load/store operations set the MMU mode to indicate that we are virtualised. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: e411c61a1452cad16853f13cac2fb86dc91ebee8.1604464950.git.alistair.francis@wdc.com
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@ -235,30 +235,31 @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
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(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
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(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_HU))) {
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get_field(env->hstatus, HSTATUS_HU))) {
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target_ulong pte;
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target_ulong pte;
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int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
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riscv_cpu_set_two_stage_lookup(env, true);
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riscv_cpu_set_two_stage_lookup(env, true);
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switch (memop) {
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switch (memop) {
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case MO_SB:
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case MO_SB:
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pte = cpu_ldsb_data_ra(env, address, GETPC());
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pte = cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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case MO_UB:
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case MO_UB:
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pte = cpu_ldub_data_ra(env, address, GETPC());
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pte = cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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case MO_TESW:
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case MO_TESW:
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pte = cpu_ldsw_data_ra(env, address, GETPC());
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pte = cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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case MO_TEUW:
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case MO_TEUW:
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pte = cpu_lduw_data_ra(env, address, GETPC());
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pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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case MO_TESL:
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case MO_TESL:
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pte = cpu_ldl_data_ra(env, address, GETPC());
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pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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case MO_TEUL:
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case MO_TEUL:
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pte = cpu_ldl_data_ra(env, address, GETPC());
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pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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case MO_TEQ:
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case MO_TEQ:
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pte = cpu_ldq_data_ra(env, address, GETPC());
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pte = cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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@ -284,23 +285,25 @@ void helper_hyp_store(CPURISCVState *env, target_ulong address,
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(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
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(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
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(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
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(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_HU))) {
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get_field(env->hstatus, HSTATUS_HU))) {
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int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
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riscv_cpu_set_two_stage_lookup(env, true);
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riscv_cpu_set_two_stage_lookup(env, true);
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switch (memop) {
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switch (memop) {
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case MO_SB:
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case MO_SB:
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case MO_UB:
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case MO_UB:
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cpu_stb_data_ra(env, address, val, GETPC());
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cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC());
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break;
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break;
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case MO_TESW:
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case MO_TESW:
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case MO_TEUW:
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case MO_TEUW:
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cpu_stw_data_ra(env, address, val, GETPC());
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cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC());
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break;
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break;
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case MO_TESL:
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case MO_TESL:
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case MO_TEUL:
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case MO_TEUL:
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cpu_stl_data_ra(env, address, val, GETPC());
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cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC());
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break;
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break;
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case MO_TEQ:
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case MO_TEQ:
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cpu_stq_data_ra(env, address, val, GETPC());
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cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC());
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break;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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@ -326,15 +329,16 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
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(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
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(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_HU))) {
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get_field(env->hstatus, HSTATUS_HU))) {
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target_ulong pte;
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target_ulong pte;
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int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
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riscv_cpu_set_two_stage_lookup(env, true);
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riscv_cpu_set_two_stage_lookup(env, true);
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switch (memop) {
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switch (memop) {
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case MO_TEUW:
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case MO_TEUW:
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pte = cpu_lduw_data_ra(env, address, GETPC());
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pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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case MO_TEUL:
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case MO_TEUL:
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pte = cpu_ldl_data_ra(env, address, GETPC());
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pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
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break;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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