target/openrisc: Implement EPH bit
Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
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@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
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if (env->cpucfgr & CPUCFGR_EVBARP) {
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if (env->cpucfgr & CPUCFGR_EVBARP) {
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vect_pc |= env->evbar;
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vect_pc |= env->evbar;
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}
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}
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if (env->sr & SR_EPH) {
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vect_pc |= 0xf0000000;
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}
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env->pc = vect_pc;
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env->pc = vect_pc;
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} else {
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} else {
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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