x86/cpu: Add AVX512_FP16 cpu feature
AVX512 Half-precision floating point (FP16) has better performance compared to FP32 if the presicion or magnitude requirements are met. It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23]. Refer to https://software.intel.com/content/www/us/en/develop/download/\ intel-architecture-instruction-set-extensions-programming-reference.html Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Message-Id: <20201216224002.32677-1-cathy.zhang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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@ -979,7 +979,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"avx512-vp2intersect", NULL, "md-clear", NULL,
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"avx512-vp2intersect", NULL, "md-clear", NULL,
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NULL, NULL, "serialize", NULL,
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NULL, NULL, "serialize", NULL,
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"tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
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"tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, "avx512-fp16",
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NULL, NULL, "spec-ctrl", "stibp",
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NULL, NULL, "spec-ctrl", "stibp",
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NULL, "arch-capabilities", "core-capability", "ssbd",
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NULL, "arch-capabilities", "core-capability", "ssbd",
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},
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},
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@ -784,6 +784,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
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#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
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/* TSX Suspend Load Address Tracking instruction */
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/* TSX Suspend Load Address Tracking instruction */
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#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
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#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
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/* AVX512_FP16 instruction */
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#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
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/* Speculation Control */
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/* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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/* Single Thread Indirect Branch Predictors */
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/* Single Thread Indirect Branch Predictors */
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