target-ppc: Add xvtstdc[sp,dp] instructions
xvtstdcsp: VSX Vector Test Data Class Single-Precision xvtstdcdp: VSX Vector Test Data Class Double-Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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00469dc373
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@ -3187,3 +3187,43 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
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}
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}
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putVSR(xT(opcode), &xt, env);
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putVSR(xT(opcode), &xt, env);
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}
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}
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/* VSX_TEST_DC - VSX floating point test data class
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* op - instruction mnemonic
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* nels - number of elements (1, 2 or 4)
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* xbn - VSR register number
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* tp - type (float32 or float64)
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* fld - vsr_t field (VsrD(*) or VsrW(*))
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* tfld - target vsr_t field (VsrD(*) or VsrW(*))
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* fld_max - target field max
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*/
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#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max) \
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void helper_##op(CPUPPCState *env, uint32_t opcode) \
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{ \
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ppc_vsr_t xt, xb; \
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uint32_t i, sign, dcmx; \
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uint32_t match = 0; \
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\
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getVSR(xbn, &xb, env); \
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memset(&xt, 0, sizeof(xt)); \
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dcmx = DCMX_XV(opcode); \
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\
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for (i = 0; i < nels; i++) { \
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sign = tp##_is_neg(xb.fld); \
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if (tp##_is_any_nan(xb.fld)) { \
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match = extract32(dcmx, 6, 1); \
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} else if (tp##_is_infinity(xb.fld)) { \
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match = extract32(dcmx, 4 + !sign, 1); \
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} else if (tp##_is_zero(xb.fld)) { \
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match = extract32(dcmx, 2 + !sign, 1); \
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} else if (tp##_is_zero_or_denormal(xb.fld)) { \
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match = extract32(dcmx, 0 + !sign, 1); \
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} \
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xt.tfld = match ? fld_max : 0; \
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match = 0; \
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} \
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putVSR(xT(opcode), &xt, env); \
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}
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VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX)
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VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX)
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@ -546,6 +546,8 @@ DEF_HELPER_2(xvcvsxdsp, void, env, i32)
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DEF_HELPER_2(xvcvuxdsp, void, env, i32)
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DEF_HELPER_2(xvcvuxdsp, void, env, i32)
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DEF_HELPER_2(xvcvsxwsp, void, env, i32)
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DEF_HELPER_2(xvcvsxwsp, void, env, i32)
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DEF_HELPER_2(xvcvuxwsp, void, env, i32)
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DEF_HELPER_2(xvcvuxwsp, void, env, i32)
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DEF_HELPER_2(xvtstdcsp, void, env, i32)
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DEF_HELPER_2(xvtstdcdp, void, env, i32)
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DEF_HELPER_2(xvrspi, void, env, i32)
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DEF_HELPER_2(xvrspi, void, env, i32)
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DEF_HELPER_2(xvrspic, void, env, i32)
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DEF_HELPER_2(xvrspic, void, env, i32)
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DEF_HELPER_2(xvrspim, void, env, i32)
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DEF_HELPER_2(xvrspim, void, env, i32)
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@ -68,7 +68,7 @@ static inline uint32_t name(uint32_t opcode) \
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((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
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((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
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}
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}
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#define EXTRACT_HELPER_DXFORM(name, \
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#define EXTRACT_HELPER_SPLIT_3(name, \
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d0_bits, shift_op_d0, shift_d0, \
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d0_bits, shift_op_d0, shift_d0, \
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d1_bits, shift_op_d1, shift_d1, \
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d1_bits, shift_op_d1, shift_d1, \
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d2_bits, shift_op_d2, shift_d2) \
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d2_bits, shift_op_d2, shift_d2) \
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@ -156,7 +156,7 @@ EXTRACT_HELPER(FPFLM, 17, 8);
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EXTRACT_HELPER(FPW, 16, 1);
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EXTRACT_HELPER(FPW, 16, 1);
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/* addpcis */
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/* addpcis */
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EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
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EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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/* darn */
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/* darn */
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EXTRACT_HELPER(L, 16, 2);
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EXTRACT_HELPER(L, 16, 2);
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@ -198,6 +198,7 @@ EXTRACT_HELPER(UIM, 16, 2);
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EXTRACT_HELPER(SHW, 8, 2);
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EXTRACT_HELPER(SHW, 8, 2);
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EXTRACT_HELPER(SP, 19, 2);
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EXTRACT_HELPER(SP, 19, 2);
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EXTRACT_HELPER(IMM8, 11, 8);
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EXTRACT_HELPER(IMM8, 11, 8);
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EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
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typedef union _ppc_vsr_t {
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typedef union _ppc_vsr_t {
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uint8_t u8[16];
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uint8_t u8[16];
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@ -928,6 +928,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
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GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
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GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
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GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
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@ -133,6 +133,14 @@ GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300),
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GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
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GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
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GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
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GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
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/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */
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#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \
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GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \
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GEN_XX3FORM(name, opc2, opc3 | 1, fl2)
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GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300),
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GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300),
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GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
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GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
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GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
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GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
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GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
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GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
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