hw/mips/cps: enable ITU for multithreading processors
Make ITU available in the system if CPU supports multithreading and is part of CPS. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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0d74a222c2
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@ -22,6 +22,7 @@
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#include "hw/mips/cps.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/cpudevs.h"
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#include "sysemu/kvm.h"
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qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
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{
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@ -56,6 +57,14 @@ static void main_cpu_reset(void *opaque)
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cs->halted = 1;
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}
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static bool cpu_mips_itu_supported(CPUMIPSState *env)
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{
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bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
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(env->CP0_Config3 & (1 << CP0C3_MT));
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return is_mt && !kvm_enabled();
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}
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static void mips_cps_realize(DeviceState *dev, Error **errp)
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{
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MIPSCPSState *s = MIPS_CPS(dev);
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@ -64,6 +73,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
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int i;
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Error *err = NULL;
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target_ulong gcr_base;
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bool itu_present = false;
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for (i = 0; i < s->num_vp; i++) {
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cpu = cpu_mips_init(s->cpu_model);
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@ -76,12 +86,34 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
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/* Init internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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if (cpu_mips_itu_supported(env)) {
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itu_present = true;
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/* Attach ITC Tag to the VP */
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env->itc_tag = mips_itu_get_tag_region(&s->itu);
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}
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qemu_register_reset(main_cpu_reset, cpu);
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}
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cpu = MIPS_CPU(first_cpu);
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env = &cpu->env;
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/* Inter-Thread Communication Unit */
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if (itu_present) {
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object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
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qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
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object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
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object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
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object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
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}
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/* Cluster Power Controller */
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object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
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qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
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@ -23,6 +23,7 @@
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#include "hw/sysbus.h"
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#include "hw/misc/mips_cmgcr.h"
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#include "hw/misc/mips_cpc.h"
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#include "hw/misc/mips_itu.h"
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#define TYPE_MIPS_CPS "mips-cps"
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#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
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@ -37,6 +38,7 @@ typedef struct MIPSCPSState {
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MemoryRegion container;
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MIPSGCRState gcr;
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MIPSCPCState cpc;
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MIPSITUState itu;
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} MIPSCPSState;
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qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
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