target/arm: Implement SVE scatter store vector immediate
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -83,6 +83,7 @@
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&rprr_gather_load rd pg rn rm esz msz u ff xs scale
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&rpri_gather_load rd pg rn imm esz msz u ff
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&rprr_scatter_store rd pg rn rm esz msz xs scale
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&rpri_scatter_store rd pg rn imm esz msz
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###########################################################################
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# Named instruction formats. These are generally used to
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@ -219,6 +220,8 @@
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&rprr_store nreg=0
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@rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
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&rprr_scatter_store
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@rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
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&rpri_scatter_store
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###########################################################################
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# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
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@ -932,6 +935,14 @@ ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
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ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
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@rprr_scatter_store xs=2 esz=3 scale=0
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# SVE 64-bit scatter store (vector plus immediate)
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ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
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@rpri_scatter_store esz=3
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# SVE 32-bit scatter store (vector plus immediate)
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ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
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@rpri_scatter_store esz=2
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# SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
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# Require msz > 0
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ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
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@ -4391,32 +4391,34 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a, uint32_t insn)
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return true;
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}
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/* Indexed by [xs][msz]. */
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static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][3] = {
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{ gen_helper_sve_stbs_zsu,
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gen_helper_sve_sths_zsu,
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gen_helper_sve_stss_zsu, },
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{ gen_helper_sve_stbs_zss,
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gen_helper_sve_sths_zss,
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gen_helper_sve_stss_zss, },
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};
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/* Note that we overload xs=2 to indicate 64-bit offset. */
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static gen_helper_gvec_mem_scatter * const scatter_store_fn64[3][4] = {
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{ gen_helper_sve_stbd_zsu,
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gen_helper_sve_sthd_zsu,
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gen_helper_sve_stsd_zsu,
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gen_helper_sve_stdd_zsu, },
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{ gen_helper_sve_stbd_zss,
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gen_helper_sve_sthd_zss,
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gen_helper_sve_stsd_zss,
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gen_helper_sve_stdd_zss, },
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{ gen_helper_sve_stbd_zd,
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gen_helper_sve_sthd_zd,
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gen_helper_sve_stsd_zd,
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gen_helper_sve_stdd_zd, },
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};
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static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
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{
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/* Indexed by [xs][msz]. */
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static gen_helper_gvec_mem_scatter * const fn32[2][3] = {
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{ gen_helper_sve_stbs_zsu,
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gen_helper_sve_sths_zsu,
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gen_helper_sve_stss_zsu, },
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{ gen_helper_sve_stbs_zss,
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gen_helper_sve_sths_zss,
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gen_helper_sve_stss_zss, },
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};
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/* Note that we overload xs=2 to indicate 64-bit offset. */
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static gen_helper_gvec_mem_scatter * const fn64[3][4] = {
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{ gen_helper_sve_stbd_zsu,
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gen_helper_sve_sthd_zsu,
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gen_helper_sve_stsd_zsu,
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gen_helper_sve_stdd_zsu, },
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{ gen_helper_sve_stbd_zss,
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gen_helper_sve_sthd_zss,
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gen_helper_sve_stsd_zss,
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gen_helper_sve_stdd_zss, },
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{ gen_helper_sve_stbd_zd,
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gen_helper_sve_sthd_zd,
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gen_helper_sve_stsd_zd,
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gen_helper_sve_stdd_zd, },
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};
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gen_helper_gvec_mem_scatter *fn;
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if (a->esz < a->msz || (a->msz == 0 && a->scale)) {
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@ -4427,10 +4429,10 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
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}
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switch (a->esz) {
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case MO_32:
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fn = fn32[a->xs][a->msz];
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fn = scatter_store_fn32[a->xs][a->msz];
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break;
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case MO_64:
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fn = fn64[a->xs][a->msz];
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fn = scatter_store_fn64[a->xs][a->msz];
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break;
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default:
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g_assert_not_reached();
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@ -4440,6 +4442,37 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
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return true;
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}
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static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
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{
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gen_helper_gvec_mem_scatter *fn = NULL;
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TCGv_i64 imm;
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if (a->esz < a->msz) {
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return false;
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}
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if (!sve_access_check(s)) {
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return true;
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}
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switch (a->esz) {
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case MO_32:
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fn = scatter_store_fn32[0][a->msz];
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break;
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case MO_64:
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fn = scatter_store_fn64[2][a->msz];
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break;
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}
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assert(fn != NULL);
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/* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x])
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* by loading the immediate into the scalar parameter.
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*/
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imm = tcg_const_i64(a->imm << a->msz);
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do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, fn);
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tcg_temp_free_i64(imm);
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return true;
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}
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/*
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* Prefetches
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*/
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