char: qemu_chr_ioctl() -> qemu_chr_fe_ioctl()
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
parent
2817822dce
commit
41084f1bad
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@ -460,7 +460,7 @@ static void escc_update_parameters(ChannelState *s)
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ssp.data_bits = data_bits;
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ssp.data_bits = data_bits;
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ssp.stop_bits = stop_bits;
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ssp.stop_bits = stop_bits;
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trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits);
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trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits);
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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}
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}
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static void escc_mem_write(void *opaque, target_phys_addr_t addr,
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static void escc_mem_write(void *opaque, target_phys_addr_t addr,
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@ -150,7 +150,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
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if (s->dataw == val)
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if (s->dataw == val)
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return;
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return;
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pdebug("wd%02x\n", val);
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pdebug("wd%02x\n", val);
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
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s->dataw = val;
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s->dataw = val;
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break;
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break;
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case PARA_REG_STS:
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case PARA_REG_STS:
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@ -170,11 +170,11 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
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} else {
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} else {
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dir = 0;
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dir = 0;
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}
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}
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
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parm &= ~PARA_CTR_DIR;
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parm &= ~PARA_CTR_DIR;
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}
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}
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
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s->control = val;
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s->control = val;
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break;
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break;
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case PARA_REG_EPP_ADDR:
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case PARA_REG_EPP_ADDR:
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@ -183,7 +183,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
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pdebug("wa%02x s\n", val);
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pdebug("wa%02x s\n", val);
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else {
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else {
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struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
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struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
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if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
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if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
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s->epp_timeout = 1;
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s->epp_timeout = 1;
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pdebug("wa%02x t\n", val);
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pdebug("wa%02x t\n", val);
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}
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}
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@ -197,7 +197,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
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pdebug("we%02x s\n", val);
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pdebug("we%02x s\n", val);
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else {
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else {
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struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
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struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
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if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
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if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
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s->epp_timeout = 1;
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s->epp_timeout = 1;
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pdebug("we%02x t\n", val);
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pdebug("we%02x t\n", val);
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}
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}
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@ -222,7 +222,7 @@ parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
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pdebug("we%04x s\n", val);
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pdebug("we%04x s\n", val);
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return;
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return;
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}
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}
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err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
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err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
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if (err) {
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if (err) {
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s->epp_timeout = 1;
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s->epp_timeout = 1;
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pdebug("we%04x t\n", val);
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pdebug("we%04x t\n", val);
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@ -245,7 +245,7 @@ parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
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pdebug("we%08x s\n", val);
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pdebug("we%08x s\n", val);
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return;
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return;
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}
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}
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err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
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err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
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if (err) {
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if (err) {
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s->epp_timeout = 1;
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s->epp_timeout = 1;
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pdebug("we%08x t\n", val);
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pdebug("we%08x t\n", val);
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@ -297,13 +297,13 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
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addr &= 7;
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addr &= 7;
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switch(addr) {
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switch(addr) {
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case PARA_REG_DATA:
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case PARA_REG_DATA:
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
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if (s->last_read_offset != addr || s->datar != ret)
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if (s->last_read_offset != addr || s->datar != ret)
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pdebug("rd%02x\n", ret);
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pdebug("rd%02x\n", ret);
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s->datar = ret;
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s->datar = ret;
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break;
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break;
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case PARA_REG_STS:
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case PARA_REG_STS:
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
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ret &= ~PARA_STS_TMOUT;
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ret &= ~PARA_STS_TMOUT;
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if (s->epp_timeout)
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if (s->epp_timeout)
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ret |= PARA_STS_TMOUT;
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ret |= PARA_STS_TMOUT;
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@ -315,7 +315,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
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/* s->control has some bits fixed to 1. It is zero only when
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/* s->control has some bits fixed to 1. It is zero only when
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it has not been yet written to. */
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it has not been yet written to. */
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if (s->control == 0) {
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if (s->control == 0) {
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
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if (s->last_read_offset != addr)
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if (s->last_read_offset != addr)
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pdebug("rc%02x\n", ret);
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pdebug("rc%02x\n", ret);
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s->control = ret;
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s->control = ret;
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@ -332,7 +332,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
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pdebug("ra%02x s\n", ret);
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pdebug("ra%02x s\n", ret);
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else {
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else {
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struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
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struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
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if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
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if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
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s->epp_timeout = 1;
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s->epp_timeout = 1;
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pdebug("ra%02x t\n", ret);
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pdebug("ra%02x t\n", ret);
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}
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}
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@ -346,7 +346,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
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pdebug("re%02x s\n", ret);
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pdebug("re%02x s\n", ret);
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else {
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else {
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struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
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struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
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if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
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if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
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s->epp_timeout = 1;
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s->epp_timeout = 1;
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pdebug("re%02x t\n", ret);
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pdebug("re%02x t\n", ret);
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}
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}
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@ -374,7 +374,7 @@ parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
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pdebug("re%04x s\n", eppdata);
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pdebug("re%04x s\n", eppdata);
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return eppdata;
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return eppdata;
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}
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}
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err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
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err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
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ret = le16_to_cpu(eppdata);
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ret = le16_to_cpu(eppdata);
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if (err) {
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if (err) {
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@ -401,7 +401,7 @@ parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
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pdebug("re%08x s\n", eppdata);
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pdebug("re%08x s\n", eppdata);
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return eppdata;
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return eppdata;
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}
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}
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err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
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err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
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ret = le32_to_cpu(eppdata);
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ret = le32_to_cpu(eppdata);
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if (err) {
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if (err) {
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@ -473,7 +473,7 @@ static int parallel_isa_initfn(ISADevice *dev)
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isa_init_irq(dev, &s->irq, isa->isairq);
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isa_init_irq(dev, &s->irq, isa->isairq);
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qemu_register_reset(parallel_reset, s);
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qemu_register_reset(parallel_reset, s);
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if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
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if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
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s->hw_driver = 1;
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s->hw_driver = 1;
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s->status = dummy;
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s->status = dummy;
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}
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}
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10
hw/serial.c
10
hw/serial.c
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@ -274,7 +274,7 @@ static void serial_update_parameters(SerialState *s)
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ssp.data_bits = data_bits;
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ssp.data_bits = data_bits;
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ssp.stop_bits = stop_bits;
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ssp.stop_bits = stop_bits;
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s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
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s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
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DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
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speed, parity, data_bits, stop_bits);
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speed, parity, data_bits, stop_bits);
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@ -287,7 +287,7 @@ static void serial_update_msl(SerialState *s)
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qemu_del_timer(s->modem_status_poll);
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qemu_del_timer(s->modem_status_poll);
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if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
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if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
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s->poll_msl = -1;
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s->poll_msl = -1;
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return;
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return;
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}
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}
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@ -467,7 +467,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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break_enable = (val >> 6) & 1;
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break_enable = (val >> 6) & 1;
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if (break_enable != s->last_break_enable) {
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if (break_enable != s->last_break_enable) {
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s->last_break_enable = break_enable;
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s->last_break_enable = break_enable;
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
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&break_enable);
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&break_enable);
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}
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}
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}
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}
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@ -482,7 +482,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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if (s->poll_msl >= 0 && old_mcr != s->mcr) {
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if (s->poll_msl >= 0 && old_mcr != s->mcr) {
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qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
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qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
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flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
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flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
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@ -491,7 +491,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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if (val & UART_MCR_DTR)
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if (val & UART_MCR_DTR)
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flags |= CHR_TIOCM_DTR;
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flags |= CHR_TIOCM_DTR;
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qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
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qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
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/* Update the modem status after a one-character-send wait-time, since there may be a response
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/* Update the modem status after a one-character-send wait-time, since there may be a response
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from the device/computer at the other end of the serial line */
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from the device/computer at the other end of the serial line */
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qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
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qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
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@ -980,7 +980,7 @@ static void strongarm_uart_update_parameters(StrongARMUARTState *s)
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ssp.stop_bits = stop_bits;
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ssp.stop_bits = stop_bits;
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s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
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s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
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if (s->chr) {
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if (s->chr) {
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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}
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}
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DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
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DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
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@ -203,7 +203,7 @@ static uint8_t usb_get_modem_lines(USBSerialState *s)
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int flags;
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int flags;
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uint8_t ret;
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uint8_t ret;
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if (qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP)
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if (qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP)
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return FTDI_CTS|FTDI_DSR|FTDI_RLSD;
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return FTDI_CTS|FTDI_DSR|FTDI_RLSD;
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ret = 0;
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ret = 0;
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@ -263,7 +263,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p,
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case DeviceOutVendor | FTDI_SET_MDM_CTRL:
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case DeviceOutVendor | FTDI_SET_MDM_CTRL:
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{
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{
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static int flags;
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static int flags;
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qemu_chr_ioctl(s->cs,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
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qemu_chr_fe_ioctl(s->cs,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
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if (value & FTDI_SET_RTS) {
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if (value & FTDI_SET_RTS) {
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if (value & FTDI_RTS)
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if (value & FTDI_RTS)
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flags |= CHR_TIOCM_RTS;
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flags |= CHR_TIOCM_RTS;
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@ -276,7 +276,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p,
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else
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else
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flags &= ~CHR_TIOCM_DTR;
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flags &= ~CHR_TIOCM_DTR;
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}
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}
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qemu_chr_ioctl(s->cs,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
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qemu_chr_fe_ioctl(s->cs,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
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break;
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break;
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}
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}
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case DeviceOutVendor | FTDI_SET_FLOW_CTRL:
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case DeviceOutVendor | FTDI_SET_FLOW_CTRL:
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@ -295,7 +295,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p,
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divisor = 1;
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divisor = 1;
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s->params.speed = (48000000 / 2) / (8 * divisor + subdivisor8);
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s->params.speed = (48000000 / 2) / (8 * divisor + subdivisor8);
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qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
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qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
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break;
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break;
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}
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}
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case DeviceOutVendor | FTDI_SET_DATA:
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case DeviceOutVendor | FTDI_SET_DATA:
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@ -324,7 +324,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p,
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DPRINTF("unsupported stop bits %d\n", value & FTDI_STOP);
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DPRINTF("unsupported stop bits %d\n", value & FTDI_STOP);
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goto fail;
|
goto fail;
|
||||||
}
|
}
|
||||||
qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
|
qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
|
||||||
/* TODO: TX ON/OFF */
|
/* TODO: TX ON/OFF */
|
||||||
break;
|
break;
|
||||||
case DeviceInVendor | FTDI_GET_MDM_ST:
|
case DeviceInVendor | FTDI_GET_MDM_ST:
|
||||||
|
|
|
@ -144,7 +144,7 @@ int qemu_chr_fe_write(CharDriverState *s, const uint8_t *buf, int len)
|
||||||
return s->chr_write(s, buf, len);
|
return s->chr_write(s, buf, len);
|
||||||
}
|
}
|
||||||
|
|
||||||
int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg)
|
int qemu_chr_fe_ioctl(CharDriverState *s, int cmd, void *arg)
|
||||||
{
|
{
|
||||||
if (!s->chr_ioctl)
|
if (!s->chr_ioctl)
|
||||||
return -ENOTSUP;
|
return -ENOTSUP;
|
||||||
|
|
|
@ -94,7 +94,7 @@ void qemu_chr_add_handlers(CharDriverState *s,
|
||||||
IOReadHandler *fd_read,
|
IOReadHandler *fd_read,
|
||||||
IOEventHandler *fd_event,
|
IOEventHandler *fd_event,
|
||||||
void *opaque);
|
void *opaque);
|
||||||
int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
|
int qemu_chr_fe_ioctl(CharDriverState *s, int cmd, void *arg);
|
||||||
void qemu_chr_generic_open(CharDriverState *s);
|
void qemu_chr_generic_open(CharDriverState *s);
|
||||||
int qemu_chr_be_can_write(CharDriverState *s);
|
int qemu_chr_be_can_write(CharDriverState *s);
|
||||||
void qemu_chr_be_write(CharDriverState *s, uint8_t *buf, int len);
|
void qemu_chr_be_write(CharDriverState *s, uint8_t *buf, int len);
|
||||||
|
|
Loading…
Reference in a new issue