haraldwolff/qemu-patch-raspberry4
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char: qemu_chr_ioctl() -> qemu_chr_fe_ioctl()

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Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori 2011-08-15 11:17:34 -05:00
parent 2817822dce
commit 41084f1bad
7 changed files with 29 additions and 29 deletions
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2
hw/escc.c
View file

@ -460,7 +460,7 @@ static void escc_update_parameters(ChannelState *s)
ssp.data_bits = data_bits; ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits; ssp.stop_bits = stop_bits;
trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits); trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits);
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
} }
static void escc_mem_write(void *opaque, target_phys_addr_t addr, static void escc_mem_write(void *opaque, target_phys_addr_t addr,

30
hw/parallel.c
View file

@ -150,7 +150,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
if (s->dataw == val) if (s->dataw == val)
return; return;
pdebug("wd%02x\n", val); pdebug("wd%02x\n", val);
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
s->dataw = val; s->dataw = val;
break; break;
case PARA_REG_STS: case PARA_REG_STS:
@ -170,11 +170,11 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
} else { } else {
dir = 0; dir = 0;
} }
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
parm &= ~PARA_CTR_DIR; parm &= ~PARA_CTR_DIR;
} }
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
s->control = val; s->control = val;
break; break;
case PARA_REG_EPP_ADDR: case PARA_REG_EPP_ADDR:
@ -183,7 +183,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
pdebug("wa%02x s\n", val); pdebug("wa%02x s\n", val);
else { else {
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
s->epp_timeout = 1; s->epp_timeout = 1;
pdebug("wa%02x t\n", val); pdebug("wa%02x t\n", val);
} }
@ -197,7 +197,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
pdebug("we%02x s\n", val); pdebug("we%02x s\n", val);
else { else {
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
s->epp_timeout = 1; s->epp_timeout = 1;
pdebug("we%02x t\n", val); pdebug("we%02x t\n", val);
} }
@ -222,7 +222,7 @@ parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
pdebug("we%04x s\n", val); pdebug("we%04x s\n", val);
return; return;
} }
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) { if (err) {
s->epp_timeout = 1; s->epp_timeout = 1;
pdebug("we%04x t\n", val); pdebug("we%04x t\n", val);
@ -245,7 +245,7 @@ parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
pdebug("we%08x s\n", val); pdebug("we%08x s\n", val);
return; return;
} }
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) { if (err) {
s->epp_timeout = 1; s->epp_timeout = 1;
pdebug("we%08x t\n", val); pdebug("we%08x t\n", val);
@ -297,13 +297,13 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
addr &= 7; addr &= 7;
switch(addr) { switch(addr) {
case PARA_REG_DATA: case PARA_REG_DATA:
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
if (s->last_read_offset != addr || s->datar != ret) if (s->last_read_offset != addr || s->datar != ret)
pdebug("rd%02x\n", ret); pdebug("rd%02x\n", ret);
s->datar = ret; s->datar = ret;
break; break;
case PARA_REG_STS: case PARA_REG_STS:
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
ret &= ~PARA_STS_TMOUT; ret &= ~PARA_STS_TMOUT;
if (s->epp_timeout) if (s->epp_timeout)
ret |= PARA_STS_TMOUT; ret |= PARA_STS_TMOUT;
@ -315,7 +315,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
/* s->control has some bits fixed to 1. It is zero only when /* s->control has some bits fixed to 1. It is zero only when
it has not been yet written to. */ it has not been yet written to. */
if (s->control == 0) { if (s->control == 0) {
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
if (s->last_read_offset != addr) if (s->last_read_offset != addr)
pdebug("rc%02x\n", ret); pdebug("rc%02x\n", ret);
s->control = ret; s->control = ret;
@ -332,7 +332,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
pdebug("ra%02x s\n", ret); pdebug("ra%02x s\n", ret);
else { else {
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
s->epp_timeout = 1; s->epp_timeout = 1;
pdebug("ra%02x t\n", ret); pdebug("ra%02x t\n", ret);
} }
@ -346,7 +346,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
pdebug("re%02x s\n", ret); pdebug("re%02x s\n", ret);
else { else {
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
s->epp_timeout = 1; s->epp_timeout = 1;
pdebug("re%02x t\n", ret); pdebug("re%02x t\n", ret);
} }
@ -374,7 +374,7 @@ parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
pdebug("re%04x s\n", eppdata); pdebug("re%04x s\n", eppdata);
return eppdata; return eppdata;
} }
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le16_to_cpu(eppdata); ret = le16_to_cpu(eppdata);
if (err) { if (err) {
@ -401,7 +401,7 @@ parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
pdebug("re%08x s\n", eppdata); pdebug("re%08x s\n", eppdata);
return eppdata; return eppdata;
} }
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le32_to_cpu(eppdata); ret = le32_to_cpu(eppdata);
if (err) { if (err) {
@ -473,7 +473,7 @@ static int parallel_isa_initfn(ISADevice *dev)
isa_init_irq(dev, &s->irq, isa->isairq); isa_init_irq(dev, &s->irq, isa->isairq);
qemu_register_reset(parallel_reset, s); qemu_register_reset(parallel_reset, s);
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1; s->hw_driver = 1;
s->status = dummy; s->status = dummy;
} }

10
hw/serial.c
View file

@ -274,7 +274,7 @@ static void serial_update_parameters(SerialState *s)
ssp.data_bits = data_bits; ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits; ssp.stop_bits = stop_bits;
s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
DPRINTF("speed=%d parity=%c data=%d stop=%d\n", DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
speed, parity, data_bits, stop_bits); speed, parity, data_bits, stop_bits);
@ -287,7 +287,7 @@ static void serial_update_msl(SerialState *s)
qemu_del_timer(s->modem_status_poll); qemu_del_timer(s->modem_status_poll);
if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
s->poll_msl = -1; s->poll_msl = -1;
return; return;
} }
@ -467,7 +467,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
break_enable = (val >> 6) & 1; break_enable = (val >> 6) & 1;
if (break_enable != s->last_break_enable) { if (break_enable != s->last_break_enable) {
s->last_break_enable = break_enable; s->last_break_enable = break_enable;
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enable); &break_enable);
} }
} }
@ -482,7 +482,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
if (s->poll_msl >= 0 && old_mcr != s->mcr) { if (s->poll_msl >= 0 && old_mcr != s->mcr) {
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
@ -491,7 +491,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
if (val & UART_MCR_DTR) if (val & UART_MCR_DTR)
flags |= CHR_TIOCM_DTR; flags |= CHR_TIOCM_DTR;
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
/* Update the modem status after a one-character-send wait-time, since there may be a response /* Update the modem status after a one-character-send wait-time, since there may be a response
from the device/computer at the other end of the serial line */ from the device/computer at the other end of the serial line */
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time); qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);

2
hw/strongarm.c
View file

@ -980,7 +980,7 @@ static void strongarm_uart_update_parameters(StrongARMUARTState *s)
ssp.stop_bits = stop_bits; ssp.stop_bits = stop_bits;
s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
if (s->chr) { if (s->chr) {
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
} }
DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,

10
hw/usb-serial.c
View file

@ -203,7 +203,7 @@ static uint8_t usb_get_modem_lines(USBSerialState *s)
int flags; int flags;
uint8_t ret; uint8_t ret;
if (qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) if (qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP)
return FTDI_CTS|FTDI_DSR|FTDI_RLSD; return FTDI_CTS|FTDI_DSR|FTDI_RLSD;
ret = 0; ret = 0;
@ -263,7 +263,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p,
case DeviceOutVendor | FTDI_SET_MDM_CTRL: case DeviceOutVendor | FTDI_SET_MDM_CTRL:
{ {
static int flags; static int flags;
qemu_chr_ioctl(s->cs,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); qemu_chr_fe_ioctl(s->cs,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
if (value & FTDI_SET_RTS) { if (value & FTDI_SET_RTS) {
if (value & FTDI_RTS) if (value & FTDI_RTS)
flags |= CHR_TIOCM_RTS; flags |= CHR_TIOCM_RTS;
@ -276,7 +276,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p,
else else
flags &= ~CHR_TIOCM_DTR; flags &= ~CHR_TIOCM_DTR;
} }
qemu_chr_ioctl(s->cs,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); qemu_chr_fe_ioctl(s->cs,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
break; break;
} }
case DeviceOutVendor | FTDI_SET_FLOW_CTRL: case DeviceOutVendor | FTDI_SET_FLOW_CTRL:
@ -295,7 +295,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p,
divisor = 1; divisor = 1;
s->params.speed = (48000000 / 2) / (8 * divisor + subdivisor8); s->params.speed = (48000000 / 2) / (8 * divisor + subdivisor8);
qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params); qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
break; break;
} }
case DeviceOutVendor | FTDI_SET_DATA: case DeviceOutVendor | FTDI_SET_DATA:
@ -324,7 +324,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p,
DPRINTF("unsupported stop bits %d\n", value & FTDI_STOP); DPRINTF("unsupported stop bits %d\n", value & FTDI_STOP);
goto fail; goto fail;
} }
qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params); qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
/* TODO: TX ON/OFF */ /* TODO: TX ON/OFF */
break; break;
case DeviceInVendor | FTDI_GET_MDM_ST: case DeviceInVendor | FTDI_GET_MDM_ST:

2
qemu-char.c
View file

@ -144,7 +144,7 @@ int qemu_chr_fe_write(CharDriverState *s, const uint8_t *buf, int len)
return s->chr_write(s, buf, len); return s->chr_write(s, buf, len);
} }
int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg) int qemu_chr_fe_ioctl(CharDriverState *s, int cmd, void *arg)
{ {
if (!s->chr_ioctl) if (!s->chr_ioctl)
return -ENOTSUP; return -ENOTSUP;

2
qemu-char.h
View file

@ -94,7 +94,7 @@ void qemu_chr_add_handlers(CharDriverState *s,
IOReadHandler *fd_read, IOReadHandler *fd_read,
IOEventHandler *fd_event, IOEventHandler *fd_event,
void *opaque); void *opaque);
int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg); int qemu_chr_fe_ioctl(CharDriverState *s, int cmd, void *arg);
void qemu_chr_generic_open(CharDriverState *s); void qemu_chr_generic_open(CharDriverState *s);
int qemu_chr_be_can_write(CharDriverState *s); int qemu_chr_be_can_write(CharDriverState *s);
void qemu_chr_be_write(CharDriverState *s, uint8_t *buf, int len); void qemu_chr_be_write(CharDriverState *s, uint8_t *buf, int len);