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hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts

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The ISCR.ISRPENDING bit is set when an external interrupt is pending.
This is true whether that external interrupt is enabled or not.
This means that we can't use 's->vectpending == 0' as a shortcut to
"ISRPENDING is zero", because s->vectpending indicates only the
highest priority pending enabled interrupt.

Remove the incorrect optimization so that if there is no pending
enabled interrupt we fall through to scanning through the whole
interrupt array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-07-23 17:21:44 +01:00
parent d4f6883912
commit 41487794f5
1 changed files with 4 additions and 5 deletions
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9
hw/intc/armv7m_nvic.c
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@ -127,15 +127,14 @@ static bool nvic_isrpending(NVICState *s)
{
int irq;
/* We can shortcut if the highest priority pending interrupt
* happens to be external or if there is nothing pending.
/*
* We can shortcut if the highest priority pending interrupt
* happens to be external; if not we need to check the whole
* vectors[] array.
*/
if (s->vectpending > NVIC_FIRST_IRQ) {
return true;
}
if (s->vectpending == 0) {
return false;
}
for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
if (s->vectors[irq].pending) {