target/mips: Refactor and fix COPY_U.<B|H|W> instructions
The old version of the helper for the COPY_U.<B|H|W> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>
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@ -877,7 +877,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
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@ -942,6 +941,9 @@ DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
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@ -1298,29 +1298,46 @@ void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
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env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
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}
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void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
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uint32_t ws, uint32_t n)
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void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd,
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uint32_t ws, uint32_t n)
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{
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n %= DF_ELEMENTS(df);
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switch (df) {
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case DF_BYTE:
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env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
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break;
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case DF_HALF:
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env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
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break;
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case DF_WORD:
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env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
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break;
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#ifdef TARGET_MIPS64
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case DF_DOUBLE:
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env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
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break;
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#endif
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default:
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assert(0);
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n %= 16;
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#if defined(HOST_WORDS_BIGENDIAN)
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if (n < 8) {
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n = 8 - n - 1;
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} else {
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n = 24 - n - 1;
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}
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#endif
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env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
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}
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void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd,
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uint32_t ws, uint32_t n)
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{
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n %= 8;
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#if defined(HOST_WORDS_BIGENDIAN)
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if (n < 4) {
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n = 4 - n - 1;
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} else {
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n = 12 - n - 1;
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}
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#endif
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env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
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}
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void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
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uint32_t ws, uint32_t n)
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{
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n %= 4;
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#if defined(HOST_WORDS_BIGENDIAN)
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if (n < 2) {
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n = 2 - n - 1;
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} else {
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n = 6 - n - 1;
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}
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#endif
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env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
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}
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void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
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@ -28297,6 +28297,11 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
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(df == DF_WORD)) {
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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#endif
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switch (MASK_MSA_ELM(ctx->opcode)) {
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case OPC_COPY_S_df:
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@ -28323,7 +28328,21 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
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break;
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case OPC_COPY_U_df:
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if (likely(wd != 0)) {
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gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
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switch (df) {
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case DF_BYTE:
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gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
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break;
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case DF_HALF:
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gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
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break;
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#if defined(TARGET_MIPS64)
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case DF_WORD:
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gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
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break;
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#endif
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default:
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assert(0);
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}
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}
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break;
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case OPC_INSERT_df:
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