tcg/ppc: Introduce Altivec registers
Altivec supports 32 128-bit vector registers, whose names are by convention v0 through v31. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -31,7 +31,7 @@
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# define TCG_TARGET_REG_BITS 32
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#endif
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#define TCG_TARGET_NB_REGS 32
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#define TCG_TARGET_NB_REGS 64
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
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@ -45,6 +45,15 @@ typedef enum {
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TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
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TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
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TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
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TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
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TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
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TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
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TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
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TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
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TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
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TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
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TCG_REG_CALL_STACK = TCG_REG_R1,
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TCG_AREG0 = TCG_REG_R27
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} TCGReg;
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@ -42,6 +42,9 @@
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# define TCG_REG_TMP1 TCG_REG_R12
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#endif
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#define TCG_VEC_TMP1 TCG_REG_V0
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#define TCG_VEC_TMP2 TCG_REG_V1
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#define TCG_REG_TB TCG_REG_R31
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#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
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@ -72,39 +75,15 @@ bool have_isa_3_00;
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#endif
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#ifdef CONFIG_DEBUG_TCG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"r0",
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"r1",
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"r2",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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"r8",
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"r9",
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"r10",
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"r11",
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"r12",
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"r13",
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"r14",
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"r15",
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"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
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"r30",
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"r31"
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static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
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"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
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"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
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"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
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};
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#endif
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@ -139,6 +118,26 @@ static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_R5,
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TCG_REG_R4,
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TCG_REG_R3,
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/* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
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TCG_REG_V2, /* call clobbered, vectors */
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TCG_REG_V3,
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TCG_REG_V4,
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TCG_REG_V5,
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TCG_REG_V6,
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TCG_REG_V7,
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TCG_REG_V8,
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TCG_REG_V9,
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TCG_REG_V10,
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TCG_REG_V11,
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TCG_REG_V12,
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TCG_REG_V13,
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TCG_REG_V14,
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TCG_REG_V15,
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TCG_REG_V16,
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TCG_REG_V17,
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TCG_REG_V18,
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TCG_REG_V19,
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};
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static const int tcg_target_call_iarg_regs[] = {
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@ -2808,6 +2807,27 @@ static void tcg_target_init(TCGContext *s)
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
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s->reserved_regs = 0;
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
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@ -2818,6 +2838,8 @@ static void tcg_target_init(TCGContext *s)
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
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#endif
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
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tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
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tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
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if (USE_REG_TB) {
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
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}
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